elevator program is not working on nexys4 artix7 fpga

[Krish]

elevator program is not working on the board and it is showing simulation properly.i am not getting where the mistake is happend.can you check the program why it is not working on the board.i thought that the mistake is in the elevator module.it is not taking any inputs according to the module.

thanks 

elevator12.txt

[D@n]

There are three common beginner mistakes that will keep simulation valid code from running on hardware.

1. Transitioning on something other than a clock
2. Using external asynchronous input values (buttons) without synchronization
3. Using buttons without debouncing them.

As a fun example, this post has some pictures of what buttons actually do when pressed and released.  It's part of a longer, four part series on the topic.

Then there's the asynchronous inputs.  The problem you can get into there is one where a bit is neither a one nor a zero: it is in what's called a metastable state.  Some of your logic might read it as a one, other of your logic might read it as a zero.  This can be a real problem when you develop your code, and it can also take a long time to find if you aren't careful.  You can usually mitigate this problem via a carefully engineered clock-domain crossing component, that clocks each input twice before it is used.

The final problem is that of the logical clock that you created.  These tend to have problems associated with them, and so I don't recommend them for beginners.  Other techniques are available for controlling the timing of events that don't then require you to use a logic clock.  If you do need a clock at a different speed from the one given, use a PLL or an MMCM for that purpose, and manage your clock domain crossing logic carefully.

Dan

[Krish]

here one thing i didnot understand is how to avoid bouncing of switches and i removed the posedge reset from the always block and i removed the clockout from the next always block.

but in sevensegment display i need a inbuilt clk to control the segments and i think i didnot make any mistake on the cdc logic as well.i still didnot getting the output on the board. Xst:528 - 

Multi-source in Unit <elevator> on signal <l_m>, i am getting error in the synthesis/implementation and i didnot get it.

can you telll me wat the error says in the photo..?????? 

 

elevator12.txt

[D@n]

@Krish,

You design is not yet ready to meet hardware.  Some problems I've found within it:

• Inside a clocked always block, always @(posedge clk), I would *HIGHLY* recommend using non-blocking assignments "<=".  Blocking assignments "=" tend to lead to simulation-hardware mismatch.
• Logic clocks, such as those created by your clockgen are bad.  They will create several ugly consequences in your code that I'll point out in a moment.  Use the system clock (100MHz) instead.  If that's too fast for you, create a synchronous strobe signal that's only on for one clock out of 50M, and then gate all of your always blocks with "always @(posedge clk) if (stb) begin /* your logic */ end".  This simple change will spare you *many* headaches.
• You cannot set the same variable in more than one always block.  Examples in your code include l_m, l_c, and l_o.  These are set in multiple always blocks.  You'll need to change that before your design will synthesize.
• Your white spaces (tabbing) don't match your logic.  As a result, you aren't seeing that several of your assignments are overriding others.  The design is therefore flawed, but because of how you have it written it is difficult to see.  (You may have forgotten a begin/end block after an else within your first case statement.)
• I'm not sure what your test bench is showing you ... your clockgen module only lets things change every 50e6 samples.
• I don't see any of the wires you list above in your design.  Not setting them will be a synthesis error if they exist within your XDC file.  Perhaps you commented them out, and this commenting is part of the problem.

Now, to your question: How to avoid bouncing of switches?  You can't keep the hardware switches from bouncing.  You can't.  They are going to bounce.  That's just part of how the hardware works.  Your code will have to deal with that, and present an unbounced input to your design.  This is called debouncing.  The bouncing discussion I linked to above shows you how to do this.  You'll also want to use your high speed clock, clk, to do this.  However, because you are using a logic clock (clkout), you are going to need to try to cross clock domains or risk metastability (bad).  This is a good reason for leaving your design in the one clock domain "clk" and *ONLY* transitioning on "clk" edges--not "clkout" edges.

Why is metastability bad?  Imagine your design working for you in the lab, and then failing when you try to show it to the instructor, and that's only *IF* it works in the lab.  A more likely scenario will be trying to chase down what's going wrong--your logic might work 90% of the time, but you'll never be able to catch that last 10% problem.

Looking over your code, you have not dealt with your CDC issue.  Your elevator module is setting things based upon the clock clkout, whereas your seven segment display needs to run off of the clock clk.  This is a clock domain crossing.  The easiest way to get rid of it will be to force all of your logic to transition on the same clock edge (clk).

I wrote this quickly, though, so ... if these comments don't make sense, please feel free to write back and ask me to clarify.

Dan

[Krish]

how to use that strobe signal in synchronous and i modified it everything and one thing i didnot understand the thing is (your white spaces (tabbing) don't match your logic.  As a result, you aren't seeing that several of your assignments are overriding others.  The design is therefore flawed, but because of how you have it written it is difficult to see.  (You may have forgotten a begin/end block after an else within your first case statement.))..???

New Text Document (4).txt

[JColvin]

Hi @Krish,

What @D@n is referring to is that there isn't any extra whitespace or tabs within each "sub" begin block. Since all the begin and end statements are in the same vertical line, it is more difficult to see what block is nested within a different block for debugging purposes. An example of how this might look is this:

begin
	//stuff
	if(/*condition*/)
		begin
		//more stuff
		end
	else
		begin
		//stuff
		end
end
	

Thanks,
JColvin

[Krish]

Okk I get it thanks@JColvin can u tell me how to use strobe signal

[D@n]

@Krish,

Sorry, I didn't see your reply earlier.  Here's an example showing how your elevator file might be reformatted (attached), and here's an article discussing the idea of using a strobe signal.  The attached ev12.v file still won't work, but it might give you an idea of how indentation (white space) might help you.

Hope this helps,

Dan

ev12.v

[Krish]

okk sir. can u say y still it not working i removed clockgen and i changed first always block and i changed it into the non-blocking statments also then where is the problem...??

[D@n]

Have you debounced the buttons yet?  or were they switches?  (I can't remember ...)

Dan

[Krish]

i understand the concept of debouncing but i am thinking how to use it on these many buttons....???   i tried it but i dont know that is correct or not please tell me that it is correct or not...????

New Text Document (5).txt

[jpeyron]

Hi @Krish,

Here is the OOB demo for the Nexys 4. It has a debouncer for the buttons. Here is a project for the nexys video that uses a vhdl debouncer with a verilog top file. These demos should help you see how to use a debouncer for the buttons.

thank you,

Jon