/*
module clockgen(reset,clk,clkout);
	parameter i=50000000;
	input reset,clk;
	output reg clkout;

	reg [25:0]counter;

	initial counter=0;
	always@(posedge clk)
	if(reset)
		clkout=0;
	else if(counter==i-1)
	begin
		counter=0;
		clkout=~clkout;
	end else
		counter=counter+1;

endmodule
*/

module elevator(en,reset,clk,out1,out2,out3,f1,f2,f3,l_m,l_o,l_c,sel);
	input en,reset,clk,out1,out2,out3,f1,f2,f3;
	output reg l_m,l_o,l_c;
	output reg [1:0]sel;
	parameter floor1=2'b01;
	parameter floor2=2'b10;
	parameter floor3=2'b11;
	parameter floor0=2'b00;

//	wire clkout;

//	clockgen m1(reset,clk,clkout);

	reg	[1:0]	present_state,next_state;

	initial
	begin
		present_state=0;
		next_state=0;
		l_m<=0;
		l_o<=0;
		l_c<=0;
	end

	always @ (posedge clk)
	if (reset == 1'b1)
	begin
		present_state = floor0;
		l_m<=0;
                l_o<=0;
                l_c<=0;
	end 
	else 
	begin
	next_state<=present_state;

	case(present_state)
	floor1:
		begin
		if(out1==1'b1 && en==1)
		begin
			if(f2==1)
			begin
				next_state=floor2;
				l_m<=((out1)&&(en)&&(f2));
				//delay(200);
				l_o<=((out1)&&(en)&&(f2));
				l_c<=((out1)&&(en)&&(f2));
				sel=2'b10;
			end else if(f3==1)
			begin
				next_state=floor3;
				l_m<=((out1)&&(en)&&(f3));
				//delay(300);
				l_o<=((out1)&&(en)&&(f3));
				l_c<=((out1)&&(en)&&(f3));
				sel<=2'b11;
			end else
				next_state=present_state;
			l_o<=((out1)&&(en));
			l_c<=((out1)&&(en));
			sel<=2'b01;
		end
	end


	floor2: begin
		if(out2==1'b1 && en==1)
		begin
			if(f3==1'b1)
			begin
				next_state=floor3;
 				l_m<=((out2)&&(en)&&(f3));
 				//delay(200);
 				l_o<=((out2)&&(en)&&(f3));
 				l_c<=((out2)&&(en)&&(f3));
 				sel<=2'b11;
			end else if(f1==1'b1)
			begin
				next_state=floor1;
 				l_m<=((out2)&&(en)&&(f2));
 				//delay(200);
 				l_o<=((out2)&&(en)&&(f2));
 				l_c<=((out2)&&(en)&&(f2));
 				sel<=2'b01;
			end else begin
				next_state=floor2;
				l_o<=((out2)&&(en));
				l_c<=((out2)&&(en));
				sel<=2'b10;
			end
		end
	end

	floor3: begin
		if(out3==1'b1 && en==1)
		begin
			if(f2==1'b1)
			begin
				next_state=floor2;
				l_m<=((out3)&&(en)&&(f2));
				//delay(200);
				l_o<=((out3)&&(en)&&(f2));
				l_c<=((out3)&&(en)&&(f2));
				sel<=2'b10;
			end else if(f1==1'b1)
			begin
				next_state=floor1;
				l_m<=((out3)&&(en)&&(f1));
				//delay(300);
				l_o<=((out3)&&(en)&&(f1));
				l_c<=((out3)&&(en)&&(f1));
				sel=2'b01;
			end else begin
				next_state=floor3;
				l_o<=((out3)&&(en));
				l_c<=((out3)&&(en));
				sel<=2'b11;
			end
		end
	end


	floor0: begin
		if(en==1'b1)
		begin
			next_state=floor1;
			sel<=2'b01;
			l_m<=(en);
			//delay(200);
		end else begin
			next_state=floor0;
			sel<=2'b00;
		end
	end

	default: begin
		next_state=floor0;
		sel<=2'b00;
		end
	endcase

	end

/*
function delay;
input [9:0]value;
//reg delay;
integer i;
begin
for(i=0;i<value;i=i+1)
begin
delay=0;
end
end
endfunction
*/


endmodule

module elevatortb();
reg en,reset,clk,out1,out2,out3,f1,f2,f3;
wire  l_m,l_o,l_c;
wire [1:0]sel;
elevator h1(en,reset,clk,out1,out2,out3,f1,f2,f3,l_m,l_o,l_c,sel);
initial  
clk=1; 
always #10 clk=~clk; 
initial 
begin 
reset=1;en=1;clk=1;
#10 reset=0;clk=1;out1=1;out2=1;out3=1;en=1;f3=1;f1=1;f2=0;
//#10 rst=0;clk=1;out2=1;en=1;f1=1; 
//#10 rst=0;clk=1;out3=0;f2=1;en=1; 
//#10 rst=0;clk=1;out3=0;f1=1;en=1; 
#100 $stop; 
end 
endmodule 



module segment(clk,display,seg,an);
	input clk;
	output [7:0]seg;
	input [63:0]display;
	reg [19:0]counter;
	output [7:0]an;
	always@(posedge clk)
		counter=counter+1;

	assign an = counter[19:17] == 3'b000 ? 8'b11111110:
  		counter[19:17] == 3'b001 ? 8'b11111101:
  		counter[19:17] == 3'b010 ? 8'b11111011:
  		counter[19:17] == 3'b011 ? 8'b11110111:
  		counter[19:17] == 3'b100 ? 8'b11101111:
  		counter[19:17] == 3'b101 ? 8'b11011111:
  		counter[19:17] == 3'b110 ? 8'b10111111:
  		8'b01111111;
  
	assign seg =counter [19:17]== 3'b000 ? display [7:0]:
		counter [19:17]== 3'b001 ? display [15:8]:
		counter [19:17]== 3'b010 ? display [23:16]:
		counter [19:17]== 3'b011 ? display [31:24]:
		counter [19:17]== 3'b100 ? display [39:32]:
		counter [19:17]== 3'b101 ? display [47:40]:
		counter [19:17]== 3'b110 ? display [55:48]:
			display [63:56];
endmodule



module interface(clk,reset,en,out1,out2,out3,f1,f2,f3,l_m,l_o,l_c,seg,an);
	input clk,reset,en,out1,out2,out3,f1,f2,f3;
	wire [1:0]sel;
	output l_m,l_o,l_c;
	output [7:0]seg;
	output [7:0]an;

	elevator p1(en,reset,clk,out1,out2,out3,f1,f2,f3,l_m,l_o,l_c,sel);
	reg [63:0] display;
	wire [7:0]a[9:0];
	//wire clkout;
	reg [7:0] l;
	assign a[0] =8'hc0;
	assign a[1] =8'hf9;
	assign a[2] =8'ha4;
	assign a[3] =8'hcf;
	assign a[4] =8'h99;
	assign a[5] =8'h92;
	assign a[6] =8'h82;
	assign a[7] =8'hf8;
	assign a[8] =8'h80;
	assign a[9] =8'h98;
	always @(*)
	begin
	//i={4'b0000,hh};
	//r={2'b00,mm};
	l={6'b000000,sel};
	display = {8'hbf,8'h8e,8'hc3,8'hc0,8'hc0,8'h88,a[l%10],8'hbf};
	end 

	segment s1(clk,display,seg,an);
endmodule




module top(clk,sw0,sw1,sw2,sw3,sw4,sw5,sw6,sw7,led1,led2,RGB1_Green,seg,an);
input clk,sw0,sw1,sw2,sw3,sw4,sw5,sw6,sw7;
output led1,led2,RGB1_Green;
//output [1:0]led3;
output [7:0]seg,an;
//elevator k1(sw0,sw1,clk,sw2,sw3,sw4,sw5,sw6,sw7,led1,led2,RGB1_Green,led3);
interface l1(clk,sw0,sw1,sw2,sw3,sw4,sw5,sw6,sw7,led1,led2,RGB1_Green,seg,an);
endmodule
//interface(clk,reset,en,out1,out2,out3,f1,f2,f3,l_m,l_o,l_c,seg,an);