Problem with "How To Store Your SDK Project in SPI Flash" tutorial

[emfries]

Hello,

 

I tried posting this on the Xilinx forums but got no response.  These forums look more active and friendly so hopefully somebody can help me.  I am really stuck.

 

I am trying to follow along with the "How To Store Your SDK Project in SPI Flash" tutorial (https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start), but I cannot get it to work.  I am using an Artix-7 35T Arty FPGA Evaluation Kit.  I am running Vivado v2017.2 (64-bit) and SDK v2017.2 on a Windows 10 machine.

 

First, I created a simple "Hello World" program by following the steps in the "Arty - Getting Started With Microblaze" tutorial (

https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-getting-started-with-microblaze/start).  The only deviation from the instructions that I made was that after adding the MIG to the board, I added an AXI Quad SPI, with enabled port SPI_0, and then ran "Run Connection Automation".  When I ran my C program on the Arty board it worked fine, and printed "Hello World" to my PuTTY terminal.  I've attached my board file as both .bd and .png.

 

Second, I tried store this "Hello World" program to the Arty's SPI Flash using the "How To Store Your SKD Project in SPI Flash" tutorial.  But, it did not work.  I'll walk you through what I did because there are a few things that I am confused about.  Unless otherwise noted I followed the instructions exactly.  Before step 0: I don't know what the QSpi mode jumper setting is referring to, so I didn't do anything.  Step 1.3: I compressed my bitstream so I left FLASH_IMAGE_BASEADDR as 0xF8000000, like I found it. Steps 2.1 and 2.2: I used my "Hello World" app that I created by following the "Arty - Getting Started with Microblaze" tutorial.  I couldn't place the sections into mig_7series_0 because that wasn't an option, so instead I used mig_7series_0_memaddr.  Step 4.1: I used offset 0xF8000000 because that is what I used in Step 1.3.  One other thing: the test says to use Arty flash type mt25ql128-spi-x1_x2_x4 (which I do), but the image of the "Program Flash Memory" window shows them using Arty flash type n25ql128-spi-x1_x2_x4.  Step 5: it doesn't work.

 

Does anyone have any suggestions?  Is the SPI Flash some sort of external hardware that I need to plug into the Arty?  Thanks in advance.

 

design_1.bd

[jpeyron]

Hi @emfries,

The JP1 is the mode jumper and should be shorted. Here is a working project I made that uses a compressed bitstream using the offset of 0x00300000. I used the beginning of the Arty - Getting Started with Microblaze Servers tutorial to set up the arty. I used step 1 to step 4.3 with a couple of changes like instead of a 25 mhz 3rd output clock it is a 50 mhz clock in the clock wizard on step 3.3. On step 4.2 do not select interrupt controller. Once you have completed step 4.3 drag the usb uart and the quad spi flash from the board tab to the block design. Connect the output clock 3 to the ext_spi_clk of the quad spi flash IP and then run connection automation. Next I created a wrapper. I then went to the How To Store Your SDK Project in SPI Flash tutorial. On step .5 I also clicked on configuration, set Configuration Rate (Mhz) to “33” and under Configuration Modes, select Master SPI x4. I then follow the How To Store Your SDK Project in SPI Flash with only one change i set the FLASH_IMAGE_BASEADDR to 0x00300000. I was able to use the PROG button to start the hello world program stored in flash as shown in the attached screen shot. 

cheers,

Jon

[armin]

On 12/9/2017 at 1:00 AM, jpeyron said:

Hi @emfries,

The JP1 is the mode jumper and should be shorted. Here is a working project I made that uses a compressed bitstream using the offset of 0x00300000. I used the beginning of the Arty - Getting Started with Microblaze Servers tutorial to set up the arty. I used step 1 to step 4.3 with a couple of changes like instead of a 25 mhz 3rd output clock it is a 50 mhz clock in the clock wizard on step 3.3. On step 4.2 do not select interrupt controller. Once you have completed step 4.3 drag the usb uart and the quad spi flash from the board tab to the block design. Connect the output clock 3 to the ext_spi_clk of the quad spi flash IP and then run connection automation. Next I created a wrapper. I then went to the How To Store Your SDK Project in SPI Flash tutorial. On step .5 I also clicked on configuration, set Configuration Rate (Mhz) to “33” and under Configuration Modes, select Master SPI x4. I then follow the How To Store Your SDK Project in SPI Flash with only one change i set the FLASH_IMAGE_BASEADDR to 0x00300000. I was able to use the PROG button to start the hello world program stored in flash as shown in the attached screen shot. 

 cheers,

Jon

By opening the project I have some errors. IIt cannot find the design files

[emfries]

Hi @jpeyron,

I've rolled this system out into production use but would like to make some minor updates to it. I'm now using the 5VDC power pin to power the ARTY board, and still have the UART connection over USB. Higher up in the thread you said (regarding starting up from flash) "...either unplug and plug in the usb cable or press the PROG button and the project should running on start up."

Are there any other ways to reset the board and reload from flash? My goal is to be able to reset the board remotely without any human presence near the board.

I can cycle the 5VDC with a computer-controlled relay, but when I try to open a new serial connection from the terminal I am unable to. It appears as if the computer is unable to see the ARTY board (maybe this is a Linux issue?). Only after unplugging and plugging back in the USB, or pressing the PROG button, can I establish a new serial connection.

Thanks,

[jpeyron]

Hi @Rob Young,

I am glad to hear that backing up to 2017.4 solved your issue. Thank you for sharing what you did to fix this issue.

cheers,

Jon

[Rob Young]

Vivado 2018 in general is acting quite unstable.  The SDK routinely crashes out without a cause in its log file.  Seems to be rather common with Windows 10 but less so with the Linux implementation.

Backing up to 2017.4 and I've stopped having SDK crashes and have been able to program the QSPI flash without incident, create a bootloader and boot into my larger test program every time.

 

[jpeyron]

Hi @Rob Young,

Here is an older getting started with microblaze tutorial that should be helpful with your project. Make sure you have installed and are using board files. Also remember to add the quad spi flash ip core with an additional 50 MHz output clock from the clocking wizard connected to the ext_spi_clk on the quad spi flash ip core.

thank you,

Jon

[Rob Young]

There is something fishy going on because I started over using 2018.2 and got it to work.

Bring the same project forward into 2018.3 and it doesn't work.  

Isn't that swell.

[Rob Young]

On 10/22/2018 at 4:40 PM, jpeyron said:

Hi @armin,

 Here is a completed and verified Arty-A7-35T project for the QSPI using Vivado 2018.2.  I added a screen shot of my tera term when loading from QSPI on the Arty-A7-35T.

cheers,

Jon 

So I've taken a look at your project and have been trying to implement something similar.  I am using an Arty A7-100T instead of the -35T so I started a fresh design.

My issue is that if I follow the steps in the above referenced guide, I can get my FPGA programmed (I know this because I've attached one LED on the Arty A7-100T board which blinks under control of a counter in the PL) from the FLASH.  

But the SREC bootloader doesn't seem to be starting after the FPGA is programmed. I know the bootloader works because I put my Hello World at the magic address inside the QSPI-FLASH and then explicitly tell the SDK to run the bootloader code, the serial port comes to life and reports on the loading of Hello World and then jumps into that code and starts executing.  

Development is with Vivado 2018.3, Windows 8 and 10 (two different PCs) both 64bit.  Tested on two Arty-A7-100Ts just in case there was some kind of board fault.

Is there something that broke in 2018.3? Or something else I should do since I'm using the -100T instead of -35T.  So far as I can tell, I'm not overwriting myself in the FLASH, the download.bit file and my hello_world.srec are far apart. The bit file is 2002kb so that's 0x001F4800 worth of space in the FLASH.  And I'm putting my Hello_world.srec out at 0x00C00000 so I shouldn't be overwriting myself anywhere.  

Suggestions?  Thanks for any help that may come.

Linky to a zipped copy of my test project.
https://drive.google.com/open?id=15lLWzbTffC-qnCvu9WO6QE2whmayol-m

[jpeyron]

Hi @armin,

 Here is a completed and verified Arty-A7-35T project for the QSPI using Vivado 2018.2.  I added a screen shot of my tera term when loading from QSPI on the Arty-A7-35T.

cheers,

Jon 

[armin]

1. 26 minutes ago, jpeyron said:

   Hi @armin,

   What fpga are you using? Are you using the board files for the FPGA? Did you update the ip cores in the Vivado 2018.2 version?

   cheers,

   Jon

   Hi Jon,

I use Arty board xc7a35t-1L. and vivado 208.2

[jpeyron]

Hi @armin,

What fpga are you using? Are you using the board files for the FPGA? Did you update the ip cores in the Vivado 2018.2 version?

cheers,

Jon

[armin]

On 10/15/2018 at 8:45 PM, jpeyron said:

Hi @armin,

What version of Vivado are you using? The project linked above was made in Vivado 2017.2. You should be able to make the project in a different version of vivado by using the two tutorials and the information linked above.

cheers,

Jon 

Hey, Jon, @jpeyron
 

 

I used 2016,3 and 2018.2. In the first version the error was due to version, and in the second one it asks for IP updates. I have a problem now and it is the version of XilIsf. it is 5.11 and in tutorial, it has been mentioned it should be at least 5.2. then there is no option to change it how can I handle it?

 

Thanks 

Armin

[jpeyron]

Hi @armin,

What version of Vivado are you using? The project linked above was made in Vivado 2017.2. You should be able to make the project in a different version of vivado by using the two tutorials and the information linked above.

cheers,

Jon 

[jpeyron]

Hi @emfries,

Glad to hear that upgrading solved the issue. Thank you for sharing what you did to resolve issue.

cheers,

Jon

[emfries]

Hi @jpeyron,

Happy holidays and sorry for the extremely long delay in getting back to you.  I had some unrelated technical issues with my computer that put me out of commission for a few weeks.  Add in the holiday season and I didn't work on this for a while.

I think I have solved the problem.  I upgraded from Vivado 2017.2 to 2017.4 and I can now store my code in the SPI Flash.

Thanks for all the help!

[jpeyron]

Hi @emfries,

I would suggest to start fresh making a new project. I would follow my Friday's post while you are making the new project. JP1 should be connected for the whole process. You should only need to program the FPGA and run->launch on hardware once with JP1 connected. Next I would make sure that you are using tera term and that you have tera term connected to the arty prior to you unplugging and plugging back in the usb cable.  In this case you do not need to press PROG. The program you put in flash should start with power up. Have you tried using the project I linked to? 

cheers,

Jon

[emfries]

Hello @jpeyron,

I still can't get it to run on pressing PROG, but have some updates.  A few changes:

1. I noticed in your board diagram that the AXI Uartlite was connected to AXI Interconnect in port M01_AXI, and AXI Quad SPI is connected to M00_AXI.  I had mine in the opposite order, so I switched the order of mine.  I don't think this makes any difference but wanted to eliminate whatever differences I could find.
2. I remade the VHDL wrapper and told Vivado not to autoupdate the wrapper
3. I uncommented the VERBOSE definition (step 1.6, https://reference.digilentinc.com/learn/programmable-logic/tutorials/htsspisf/start) to see if I could get error/any messages.

I removed the JP1 jumper so it was not shorted, and pressed PROG.  This wiped the FPGA and turned the DONE LED off.  Then, from the SDK and with the JP1 jumper still removed, I programmed the FPGA with hello_world.elf and ran System Debugger. I got the following output (in line 3, the hex value counted up from 00000000 to 00000103, and then the lines 4 and 5 were printed):

SREC SPI Bootloader
Loading SREC image from flash @ address: 00300000
Bootloader: Processed (0x)00000103 S-records
Executing program starting at address: 00000000
Hello World

At this point I hoped that all I needed to do was "prime the pump", so I reattached the JP1 jumper, pressed PROG to program the FPGA from the SPI, and... nothing.  Then I went back to the SDK and ran System Debugger, and got the following output:

SREC SPI Bootloader
Loading SREC image from flash @ address: 00300000
ERROR in SREC line: 00000001SREC line is corrupted

I repeated this process and got the same results.  With the JP1 jumper attached, I then unplugged the Arty and plugged it back in and established a new serial connection.  When I press PROG nothing happens (other than the DONE LED flashing off and back on).  When I go back to the SDK, do NOT program the FPGA, and run System Debugger from the SDK I get the same error message as above.

I tried the solution that the OP of this thread said worked for him, but I still get the same error message.

Any thoughts on this?

Thanks for all the help.

[jpeyron]

Hi @emfries,

If you have follow my post then you should not need to use the skd to program the Arty every time but just the once. You need to have the jumper JP1 shorted and then either unplug and plug in the usb cable or press the PROG button and the project should running on start up.

cheers,

Jon

[emfries]

Hi @jpeyron,

That worked!  Thanks for the help!  I'll work on porting this solution to my existing project.  I do have one additional question...

Now when I unplug my Arty board and plug it back in, the DONE LED lights up.  Then in the SDK I have to manually run "System Debugger using Debug_Hello_World.elf on Local" in order to get "Hello World" printed to my terminal.  Is there a way to have my program run without manually starting it from the SDK?  My goal is to plug in the Arty, establish a serial connection, and have Arty start listening for serial input, all without using Vivado or the SDK.

Thanks again!

[emfries]

Hi @jpeyron,

Sorry for the delay in getting back to you.  I think that I've made some progress.  However, the matter is still not completely resolved.

First, I think I figured out what the QSpi mode jumper is.  It's the jumper on JP1, right?  So when I want to program to QSPI Flash I should have the jumper installed.

Second, I think I got *something* to be programmed to the QSPI flash but I'm not sure how to run it, or there is some other problem.  When compressing my bitstream in "How To Store Your SDK Project in SPI Flash", during step 0.3  I added in steps 2.6 and 2.7 from "Arty Programing Guide" before selecting OK until the windows are closed.  Then I finished out the "SPI Flash" tutorial.

Third, the results.  Now when I press the PROD button with JP1 installed, the DONE LED goes dark for < 1 second and then lights up again.  When I press PROD with JP1 removed, the DONE LED turns and stays dark.  Then when I reinstall JP1 and press PROD, the DONE LED turns on and stays on.  However, nothing gets printed to my PuTTY terminal (I am trying to do Hello World).  When I run my SDK Hello World over JTAG it works fine.

Any ideas on what could be causing this?

Thanks,

[Notarobot]

@emfries

I am not familiar with Cmod7, however, you may try my checklist I used on Zybo board. The project name is Zybo_example and SDK app is called Hello.

Programming Zybo using QSPI Flash
1.    Create a base zynq design and verify.
2.    Generate the top wrapper from the block design and don't let vivado auto update the wrapper.
1.    Bitstream Settings -> check [bin_file ].
2.    Configure additional bitstream settings highlighted in blue at the top of the window. On the following window change the property Enable Bitstream Compresssion to TRUE then select OK until both windows are closed.
3.    Generate bitstream
4.    File -> export -> hardware (include bitstream)
5.    Open sdk
3.    File-> new -> application project, create new name
4.    Select FSBL and create FSBL project
5.    Update the BSP to use the updated version of xilisf. To do this, right click on the BSP and select Board Support Package settings and make sure that xilisf is checked
6.    Xilinx tools-> create boot image
a.    Choose .bif file output location inside work directory
b.    Partition type: bootloader add <FSBL>.elf -> \\UserX\Zybo_example\Zybo_example.sdk\Hello\Debug\Hello.elf
c.    Partition type: datafile add hardware .bit file ->   \\UserX\Zybo_example\Zybo_example.sdk\design_1_wrapper_hw_platform_0\design_1_wrapper.bit
d.    Partition type: datafile add SDK C-application .elf file -> \\UserX\Zybo_example\Zybo_example.sdk\Hello\Debug\Hello.elf
7.    Click create image
8.    SDK Xilinx tools -> program flash and choose created .bin file
9.    Switch jumper from JTAG to QSPI
10.    Cycle power to boot from QSPI

Good luck!

[jpeyron]

Hi @emfries,

I know you can use the offset of 0x00C00000. Here is a forum thread that discusses using a compressed bitstream for the Cmod A7 that might have some good offsets for the Arty as well. I have suggested more information for compressed offsets to be provided in the How to store your SDK project in flash tutorial to our content team. This tutorial was made before Vivado 2017.1 which is when the flash type to be used changed to mt25ql128-spi-x1_x2_x4 as you can see in the reference manual the flash type is N25Q128A13ESF40. 

thank you,

Jon