xilinx.com
BlockDiagram
design_1
1.00.a
isTop
true
ddr3_sdram
qspi_flash
usb_uart
CLK.SYS_CLOCK
Clk
Clock
CLK
sys_clock
FREQ_HZ
100000000
PHASE
0.000
RST.RESET
Reset
Reset
RST
reset
POLARITY
ACTIVE_LOW
BlockDiagram
:vivado.xilinx.com:
sys_clock
in
reset
in
xilinx.com
BlockDiagram
design_1_imp
1.00.a
clk_wiz_0
design_1_clk_wiz_0_1
true
2
166.667
200.000
resetn
1
6.000
5
ACTIVE_LOW
true
sys_clock
reset
118.758
114.829
98.575
mig_7series_0
design_1_mig_7series_0_1
reset
ddr3_sdram
axi_quad_spi_0
design_1_axi_quad_spi_0_1
true
qspi_flash
microblaze_0
design_1_microblaze_0_2
1
1
1
1
1
16384
1
16384
microblaze_0_local_memory
mdm_1
design_1_mdm_1_2
rst_mig_7series_0_83M
design_1_rst_mig_7series_0_83M_2
axi_uartlite_0
design_1_axi_uartlite_0_2
true
usb_uart
axi_smc
design_1_axi_smc_1
2
microblaze_0_axi_periph
design_1_microblaze_0_axi_periph_1
2
xilinx.com:ip:axi_interconnect:2.1
microblaze_0_dlmb_1
microblaze_0_ilmb_1
microblaze_0_debug
microblaze_0_M_AXI_DC
axi_smc_M00_AXI
microblaze_0_M_AXI_IC
microblaze_0_M_AXI_DP
microblaze_0_axi_periph_M00_AXI
microblaze_0_axi_periph_M01_AXI
sys_clock_1
clk_wiz_0_clk_out1
clk_wiz_0_clk_out2
reset_1
microblaze_0_Clk
mig_7series_0_mmcm_locked
mig_7series_0_ui_clk_sync_rst
rst_mig_7series_0_83M_mb_reset
rst_mig_7series_0_83M_bus_struct_reset
mdm_1_debug_sys_rst
rst_mig_7series_0_83M_peripheral_aresetn
rst_mig_7series_0_83M_interconnect_aresetn
xilinx.com
BlockDiagram/design_1_imp
microblaze_0_axi_periph
1.00.a
S00_AXI
M00_AXI
M01_AXI
CLK.ACLK
Clk
Clock
CLK
ACLK
ASSOCIATED_RESET
ARESETN
RST.ARESETN
Reset
Reset
RST
ARESETN
CLK.S00_ACLK
Clk
Clock
CLK
S00_ACLK
ASSOCIATED_BUSIF
S00_AXI
ASSOCIATED_RESET
S00_ARESETN
RST.S00_ARESETN
Reset
Reset
RST
S00_ARESETN
CLK.M00_ACLK
Clk
Clock
CLK
M00_ACLK
ASSOCIATED_BUSIF
M00_AXI
ASSOCIATED_RESET
M00_ARESETN
RST.M00_ARESETN
Reset
Reset
RST
M00_ARESETN
CLK.M01_ACLK
Clk
Clock
CLK
M01_ACLK
ASSOCIATED_BUSIF
M01_AXI
ASSOCIATED_RESET
M01_ARESETN
RST.M01_ARESETN
Reset
Reset
RST
M01_ARESETN
BlockDiagram
:vivado.xilinx.com:
ACLK
in
ARESETN
in
S00_ACLK
in
S00_ARESETN
in
M00_ACLK
in
M00_ARESETN
in
M01_ACLK
in
M01_ARESETN
in
xilinx.com
BlockDiagram/design_1_imp
microblaze_0_axi_periph_imp
1.00.a
xbar
design_1_xbar_1
1
2
0
s00_couplers
m00_couplers
m01_couplers
s00_couplers_to_xbar
xbar_to_m00_couplers
xbar_to_m01_couplers
microblaze_0_axi_periph_ACLK_net
microblaze_0_axi_periph_ARESETN_net
S00_ACLK_1
S00_ARESETN_1
M00_ACLK_1
M00_ARESETN_1
M01_ACLK_1
M01_ARESETN_1
xilinx.com
BlockDiagram/design_1_imp/microblaze_0_axi_periph_imp
m01_couplers
1.00.a
M_AXI
S_AXI
CLK.M_ACLK
Clk
Clock
CLK
M_ACLK
ASSOCIATED_BUSIF
M_AXI
ASSOCIATED_RESET
M_ARESETN
RST.M_ARESETN
Reset
Reset
RST
M_ARESETN
CLK.S_ACLK
Clk
Clock
CLK
S_ACLK
ASSOCIATED_BUSIF
S_AXI
ASSOCIATED_RESET
S_ARESETN
RST.S_ARESETN
Reset
Reset
RST
S_ARESETN
BlockDiagram
:vivado.xilinx.com:
M_ACLK
in
M_ARESETN
in
S_ACLK
in
S_ARESETN
in
xilinx.com
BlockDiagram/design_1_imp/microblaze_0_axi_periph_imp
m01_couplers_imp
1.00.a
xilinx.com
BlockDiagram/design_1_imp/microblaze_0_axi_periph_imp
m00_couplers
1.00.a
M_AXI
S_AXI
CLK.M_ACLK
Clk
Clock
CLK
M_ACLK
ASSOCIATED_BUSIF
M_AXI
ASSOCIATED_RESET
M_ARESETN
RST.M_ARESETN
Reset
Reset
RST
M_ARESETN
CLK.S_ACLK
Clk
Clock
CLK
S_ACLK
ASSOCIATED_BUSIF
S_AXI
ASSOCIATED_RESET
S_ARESETN
RST.S_ARESETN
Reset
Reset
RST
S_ARESETN
BlockDiagram
:vivado.xilinx.com:
M_ACLK
in
M_ARESETN
in
S_ACLK
in
S_ARESETN
in
xilinx.com
BlockDiagram/design_1_imp/microblaze_0_axi_periph_imp
m00_couplers_imp
1.00.a
xilinx.com
BlockDiagram/design_1_imp/microblaze_0_axi_periph_imp
s00_couplers
1.00.a
M_AXI
S_AXI
CLK.M_ACLK
Clk
Clock
CLK
M_ACLK
ASSOCIATED_BUSIF
M_AXI
ASSOCIATED_RESET
M_ARESETN
RST.M_ARESETN
Reset
Reset
RST
M_ARESETN
CLK.S_ACLK
Clk
Clock
CLK
S_ACLK
ASSOCIATED_BUSIF
S_AXI
ASSOCIATED_RESET
S_ARESETN
RST.S_ARESETN
Reset
Reset
RST
S_ARESETN
BlockDiagram
:vivado.xilinx.com:
M_ACLK
in
M_ARESETN
in
S_ACLK
in
S_ARESETN
in
xilinx.com
BlockDiagram/design_1_imp/microblaze_0_axi_periph_imp
s00_couplers_imp
1.00.a
xilinx.com
BlockDiagram/design_1_imp
microblaze_0_local_memory
1.00.a
DLMB
ILMB
CLK.LMB_CLK
Clk
Clock
CLK
LMB_Clk
RST.SYS_RST
Reset
Reset
RST
SYS_Rst
BlockDiagram
:vivado.xilinx.com:
LMB_Clk
in
SYS_Rst
in
xilinx.com
BlockDiagram/design_1_imp
microblaze_0_local_memory_imp
1.00.a
dlmb_v10
design_1_dlmb_v10_2
ilmb_v10
design_1_ilmb_v10_2
dlmb_bram_if_cntlr
design_1_dlmb_bram_if_cntlr_2
0
ilmb_bram_if_cntlr
design_1_ilmb_bram_if_cntlr_2
0
lmb_bram
design_1_lmb_bram_2
True_Dual_Port_RAM
BRAM_Controller
microblaze_0_dlmb_bus
microblaze_0_ilmb_bus
microblaze_0_dlmb_cntlr
microblaze_0_ilmb_cntlr
microblaze_0_Clk
SYS_Rst_1
xilinx.com
Addressing/microblaze_0
microblaze
10.0
Data
4G
32
SEG_axi_quad_spi_0_Reg
/axi_quad_spi_0/AXI_LITE/Reg
0x44A00000
64K
SEG_axi_uartlite_0_Reg
/axi_uartlite_0/S_AXI/Reg
0x40600000
64K
SEG_dlmb_bram_if_cntlr_Mem
/microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem
0x00000000
32K
SEG_mig_7series_0_memaddr
/mig_7series_0/memmap/memaddr
0x80000000
256M
Instruction
4G
32
SEG_ilmb_bram_if_cntlr_Mem
/microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem
0x00000000
32K
SEG_mig_7series_0_memaddr
/mig_7series_0/memmap/memaddr
0x80000000
256M
xilinx.com
Addressing/mdm_1
mdm
3.2