I am using a zybo-Z7-20 board and specifying VHDL. I have successfully completed the design and can modify the 'C' code in the xilinx SDK using the zynq processor. I am having trouble attempting to complete the same feat using a MicroBlaze processor.
The fatal problem occurs in step 5.3 when generating the Bitstream. In various attempts the errors center around 2 unassigned ports. Here is the latest.
[DRC NSTD-1] Unspecified I/O Standard: 2 out of 11 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value.
[DRC UCIO-1] Unconstrained Logical Port: 2 out of 11 logical ports have no user assigned specific location constraint (LOC).
I have attached the full error and block design.
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I wish to add a couple of comments regarding Vivado. In my installation on two different computers; in step 5.2 when defining the Top Module, the 5.2 recipe does not work for me on these two Windows installations. However, if one exits Vivado and restarts Vivado, the top module magically appears. However, if one starts Vivado from its desktop icon, Vivado get confused as to what is its project name. If one starts Vivado at this point from the file name in the project directory (ProjectName.xpr) the problem goes away. (See attachment VivadoProjName.JPG, project name is GettingStarted_3)
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rzsmi
I am following the steps outlined in https://reference.digilentinc.com/vivado/getting-started-with-ipi/start
I am using a zybo-Z7-20 board and specifying VHDL. I have successfully completed the design and can modify the 'C' code in the xilinx SDK using the zynq processor. I am having trouble attempting to complete the same feat using a MicroBlaze processor.
The fatal problem occurs in step 5.3 when generating the Bitstream. In various attempts the errors center around 2 unassigned ports. Here is the latest.
[DRC NSTD-1] Unspecified I/O Standard: 2 out of 11 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value.
[DRC UCIO-1] Unconstrained Logical Port: 2 out of 11 logical ports have no user assigned specific location constraint (LOC).
I have attached the full error and block design.
----
I wish to add a couple of comments regarding Vivado. In my installation on two different computers; in step 5.2 when defining the Top Module, the 5.2 recipe does not work for me on these two Windows installations. However, if one exits Vivado and restarts Vivado, the top module magically appears. However, if one starts Vivado from its desktop icon, Vivado get confused as to what is its project name. If one starts Vivado at this point from the file name in the project directory (ProjectName.xpr) the problem goes away. (See attachment VivadoProjName.JPG, project name is GettingStarted_3)
GettingStarted_error.txt
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