Pin Planning (2 errors)
[DRC NSTD-1] Unspecified I/O Standard: 2 out of 11 logical ports use I/O standard 
(IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may 
cause I/O contention or incompatibility with the board power or connectivity 
affecting performance, signal integrity or in extreme cases cause damage to the 
device or the components to which it is connected. To correct this violation, 
specify all I/O standards. This design will fail to generate a bitstream unless 
all logical ports have a user specified I/O standard value defined. To allow 
bitstream creation with unspecified I/O standard values (not recommended), use this 
command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using 
the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to 
a .tcl file and add that file as a pre-hook for write_bitstream step for the 
implementation run. Problem ports: reset_rtl_0, and reset_rtl.

[DRC UCIO-1] Unconstrained Logical Port: 2 out of 11 logical ports have no user 
assigned specific location constraint (LOC). This may cause I/O contention or 
incompatibility with the board power or connectivity affecting performance, 
signal integrity or in extreme cases cause damage to the device or the components 
to which it is connected. To correct this violation, specify all pin locations. 
This design will fail to generate a bitstream unless all logical ports have a user 
specified site LOC constraint defined.  To allow bitstream creation with unspecified 
pin locations (not recommended), use this command: set_property SEVERITY {Warning} 
[get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure 
(e.g. launch_runs Tcl command), add this command to a .tcl file and add that file 
as a pre-hook for write_bitstream step for the implementation run.  Problem ports: 
reset_rtl_0, and reset_rtl.

[Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
Pin Planning