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Sami Malik

unable to instantiate my verilog file in design_wrapper

Question

Hi

i am working on a project in which I have to take output from bram and turn on leds on ZYBO using custom IP.  So far I am able to write on BRAM from PS section and read it from PL section of ZYBO with my custom IP. I want to connect the data coming out of my custom IP with my on board LEDs of zybo without interfacing AXI_GPIO. For this purpose I set the output of my custom IP as external and wrote a verilog module in which I'm trying to get data of my external port on the basis of which i am switching on and off the LEDs by instantiating it with design_wrapper. But it is giving the error on my external port while generating Bitstream. How can I overcome it and is there any alternate way to do that?

screenshot of my design errors, verilog module are attached below.

Regards,

here.png

here1.png

New Text Document (11).txt

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Hi @Sami Malik,

If you are wanting to send the data from dout to your on-board leds then you will need to alter your xdc constraints to :

##LEDs
set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { ldout[0] }]; #IO_L23P_T3_35 Sch=LED0
set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { dout[1] }]; #IO_L23N_T3_35 Sch=LED1
set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { dout[2] }]; #IO_0_35=Sch=LED2
set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { dout[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=LED3

In your wrapper I also saw a pin labeled led. Where are you getting these pins in the block design?

thank you,

Jon


 

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Hi @jpeyron,

Sir I don't know the exact procedure to instantiate my verilog module in wrapper. Actually sir I want the data coming out of dout to be utilized in my main verilog file. For this purpose I thought let's start from basic which is to switch on and off the LEDs with the help of data coming out from dout. But changing the xdc file for my purpose will may be not help me out. I want to instantiate a verilog module in wrapper which will be doing the same task. My all approach to do so is given above even my verilog module. Maybe now you will be able to help me out more accurately. 

Thanks for your reply sir.

Regards,

Sami

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Hi @Sami Malik,

 If the verilog module you are instantiating  is only working with standard signals like dout then I don not see a reason you would not be able to add an instantiation to the vivado created wrapper.

If the signals you are trying to work with a on the axi bus then you will either have to facilitate communication between the axi bus and the verilog module which is a complicated task.

The other way is to use the add a module function in the block design and vivado facilitates the communication with your verilog module and the axi bus. Here is a forum thread about using the add a module function.

thank you,

Jon

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Hi @jpeyron

I am just transferring data of dout to my verilog module using instensiation of my verilog module in top level Wrapper but I think I don't know the exact procedure to do so as I have attached above my work that I have carried out until now. In above attachments I showed that I want to switch on LEDs to start from basic but changing xdc file will not lead me to my solution.

Thanks. 

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Hi @Sami Malik,

Here is a basic keyboard project using verilog. The top file here shows how to use wires and registers to connect signals from one instance to another. So for your module you would want something like below:

instens_module  your_module (

.clk (clk ),

.din(dout),

.led (led)

);

 

cheers,

Jon

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Hi @jpeyron

Thank you sir for your time. If you are going to make a project then let me try to explain it once again.

Actually sir I have written a verilog module(VGA.v) which will be controlling my vga port. I also have some data in my PS section of ZYBO, that I want to transfer to my verilog module(VGA.v). For this purpose I am transferring data from PS -> dual port BRAM -> my custom IP.  Basically I am using a custom IP so that I will take the data coming from PS section and Transfer it to my verilog module(VGA.v) by instantiating my IP to my verilog module. 

Regards,

Sami

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Hi @Sami Malik,

I do not have the bandwidth to make your project but I do have bandwidth to alter 4 signals coming from an axi-gpio with the gpio out set to custom to your verilog module. I do not have Vivado 2014.4 as your other thread here states you are using. I decided to use Vivado 2016.4 since  the HDMI IN was done for this version. 

The HDMI IN attached below for the zybo in vivado 2016.4 has gpio IP cores for the on-board leds, buttons and switches. The sdk project does not use them but they are in the project. I used your verilog module and the add  module function in the block design to send the 4 pins that would have been for the on-board leds through the board files(set the gpio out to custom) to the verilog module and constrained the led pins in the xdc. Here is the altered HDMI-IN Zybo Vivado 2-16.4 folder and the actual project is in the proj folder.

Depending on what information in the PS you are trying to manipulate we do have a VHDL VGA project i attached below for the ZYBO that might be useful.

Also here is a  forum that has a Vivado 2014.4 Zybo pass through project here using the DVI2RGB and RGB2VGA IP cores which can be found in Digilent's Vivado library here.

thank you,

Jon

top.vhd

ZYBO_Master.xdc

Zybo_hdmi_in_altered.jpg

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