i am working on a project in which I have to take output from bram and turn on leds on ZYBO using custom IP. So far I am able to write on BRAM from PS section and read it from PL section of ZYBO with my custom IP. I want to connect the data coming out of my custom IP with my on board LEDs of zybo without interfacing AXI_GPIO. For this purpose I set the output of my custom IP as external and wrote a verilog module in which I'm trying to get data of my external port on the basis of which i am switching on and off the LEDs by instantiating it with design_wrapper. But it is giving the error on my external port while generating Bitstream. How can I overcome it and is there any alternate way to do that?
screenshot of my design errors, verilog module are attached below.
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Sami Malik
Hi
i am working on a project in which I have to take output from bram and turn on leds on ZYBO using custom IP. So far I am able to write on BRAM from PS section and read it from PL section of ZYBO with my custom IP. I want to connect the data coming out of my custom IP with my on board LEDs of zybo without interfacing AXI_GPIO. For this purpose I set the output of my custom IP as external and wrote a verilog module in which I'm trying to get data of my external port on the basis of which i am switching on and off the LEDs by instantiating it with design_wrapper. But it is giving the error on my external port while generating Bitstream. How can I overcome it and is there any alternate way to do that?
screenshot of my design errors, verilog module are attached below.
Regards,
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