Basys 3 Bitstream Generation Error

[ulvarg]

Hi, 

 

I recently acquired a Basys 3 board and am currently trying to run the abacus demo on the board with a .bin file. I have been able to synthesize and implement all of the verilog files and followed all of the steps given in the demonstration video to run the project on the board , but I have not been able to generate the bitstream file. I attached a report file just in case someone wants to take a look at it.

EDIT: I have found three errors but do not know what they mean.
 

[Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 1 out of 50 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk.

[Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 1 out of 50 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: clk.

 

 

[Vivado 12-1345] Error(s) found during DRC. Bitgen not run.

 

bitstream_report.txt

[ulvarg]

I already figured out what my error was. If anyone else finds himself/herself in a situation where the bitstream file gives the errors I listed above,  just enable the clock pins on the Basys 3 XDC file.

[JColvin]

Thank you for sharing your solution!

[ashkan]

I already figured out what my error was. If anyone else finds himself/herself in a situation where the bitstream file gives the errors I listed above,  just enable the clock pins on the Basys 3 XDC file.

Hello Ulvarg, I am having the same problem. What do you mean by enabling clock pin? if you mean writing set property commands, can you write them here to show me?

[ulvarg]

You should see the following lines somewhere in your XDC file:

## Clock signal
#set_property PACKAGE_PIN W5 [get_ports clk]							
	#set_property IOSTANDARD LVCMOS33 [get_ports clk]
	#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]

Just take out the hashtags (#) in order to enable the clock pin. 

 

[psglucky]

Hi guys,

Please am working on this design from the repository here (https://github.com/forconesi/HW-Flow-Based-Monitoring/tree/master/NF_BRAM/flow_cache_v1_00_a/hdl/vhdl). Am trying to implement it on a ZedBoard using vivado 2014.2. But when I run the synthesis and implementations, it displays 'Bitstream Generation failed' and below are the details.

 

[DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 144 out of 144 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: S_AXIS_TDATA[63:0], M_AXIS_EXP_RECORDS_TDATA[63:0], M_AXIS_EXP_RECORDS_TSTRB[7:0], ACLK, ARESETN, S_AXIS_TREADY, S_AXIS_TLAST, S_AXIS_TVALID, M_AXIS_EXP_RECORDS_TVALID, M_AXIS_EXP_RECORDS_TLAST, M_AXIS_EXP_RECORDS_TREADY.

 

[Vivado 12-1345] Error(s) found during DRC. Bitgen not run.

 

With a couple of other warnings.

 

Please can someone help me check it out to see what am doing wrong because am very new to design on vivado and Zedboards generally.

Any help is appreciated.

Thanks guys.

[Bianca]

Hello @psglucky,

I am not very sure what you have there but giving the fact that you have a number so large of ports I'm guessing that you are compiling a wrong Top level. Maybe this one should be internal. 

Make sure you have the correct top level selected and that the XDC is set accordingly to your project.

Maybe someone will see something that I'm missing and could add something or give you another perspective.

Best regards,

Bianca

[D@n]

@psglucky,

If 144 out of 144 I/O ports are assigned to IOSTANDARD DEFAULT, then you either have 1. No XDC file, or 2. an XDC file that doesn't match your top level.

Take a look at your XDC file (or lack thereof), 'cause that's where your problem is at.

Dan