#----------------------------------------------------------- # Vivado v2014.3.1 (64-bit) # SW Build 1056140 on Thu Oct 30 17:03:40 MDT 2014 # IP Build 1028902 on Fri Sep 26 17:35:13 MDT 2014 # Start of session at: Thu Nov 20 18:49:36 2014 # Process ID: 8172 # Log file: C:/Users/Owner/Desktop/Verilog_Practice/project_1/project_1.runs/impl_1/Basys3_Abacus_Top.vdi # Journal file: C:/Users/Owner/Desktop/Verilog_Practice/project_1/project_1.runs/impl_1\vivado.jou #----------------------------------------------------------- source Basys3_Abacus_Top.tcl -notrace Command: open_checkpoint C:/Users/Owner/Desktop/Verilog_Practice/project_1/project_1.runs/impl_1/Basys3_Abacus_Top.dcp INFO: [Netlist 29-17] Analyzing 79 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2014.3.1 Loading clock regions from C:/Xilinx/Vivado/2014.3.1/data\parts/xilinx/artix7/artix7/xc7a35t/ClockRegion.xml Loading clock buffers from C:/Xilinx/Vivado/2014.3.1/data\parts/xilinx/artix7/artix7/xc7a35t/ClockBuffers.xml Loading clock placement rules from C:/Xilinx/Vivado/2014.3.1/data/parts/xilinx/artix7/ClockPlacerRules.xml Loading package pin functions from C:/Xilinx/Vivado/2014.3.1/data\parts/xilinx/artix7/PinFunctions.xml... Loading package from C:/Xilinx/Vivado/2014.3.1/data\parts/xilinx/artix7/artix7/xc7a35t/cpg236/Package.xml Loading io standards from C:/Xilinx/Vivado/2014.3.1/data\./parts/xilinx/artix7/IOStandards.xml Loading device configuration modes from C:/Xilinx/Vivado/2014.3.1/data\parts/xilinx/artix7/ConfigModes.xml INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [C:/Users/Owner/Desktop/Verilog_Practice/project_1/project_1.runs/impl_1/.Xil/Vivado-8172-Owner/dcp/Basys3_Abacus_Top.xdc] Finished Parsing XDC File [C:/Users/Owner/Desktop/Verilog_Practice/project_1/project_1.runs/impl_1/.Xil/Vivado-8172-Owner/dcp/Basys3_Abacus_Top.xdc] Reading XDEF placement. Reading placer database... Reading XDEF routing. Read XDEF File: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.187 . Memory (MB): peak = 446.719 ; gain = 0.000 Restored from archive | CPU: 0.000000 secs | Memory: 0.000000 MB | Finished XDEF File Restore: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.187 . Memory (MB): peak = 446.719 ; gain = 0.000 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Project 1-484] Checkpoint was created with build 1056140 open_checkpoint: Time (s): cpu = 00:00:06 ; elapsed = 00:00:15 . Memory (MB): peak = 446.719 ; gain = 270.523 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' INFO: [Drc 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command opt_design Starting DRC Task INFO: [Drc 23-27] Running DRC with 2 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.282 . Memory (MB): peak = 448.543 ; gain = 0.750 INFO: [Timing 38-35] Done setting XDC timing constraints. Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 1 Retarget | Checksum: 23a8f92e9 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.420 . Memory (MB): peak = 929.320 ; gain = 0.000 Phase 2 Constant Propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-10] Eliminated 97 cells. Phase 2 Constant Propagation | Checksum: 17c10b76f Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 929.320 ; gain = 0.000 Phase 3 Sweep INFO: [Opt 31-12] Eliminated 255 unconnected nets. INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers. INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers. INFO: [Opt 31-11] Eliminated 0 unconnected cells. Phase 3 Sweep | Checksum: 19e526719 Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 929.320 ; gain = 0.000 Ending Logic Optimization Task | Checksum: 19e526719 Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 929.320 ; gain = 0.000 Implement Debug Cores | Checksum: 23a8f92e9 Logic Optimization | Checksum: 23a8f92e9 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 3.13 ns. Ending Power Optimization Task | Checksum: 19e526719 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.149 . Memory (MB): peak = 929.320 ; gain = 0.000 INFO: [Common 17-83] Releasing license: Implementation 25 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:18 ; elapsed = 00:00:32 . Memory (MB): peak = 929.320 ; gain = 482.602 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.101 . Memory (MB): peak = 929.320 ; gain = 0.000 INFO: [Drc 23-27] Running DRC with 2 threads INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Owner/Desktop/Verilog_Practice/project_1/project_1.runs/impl_1/Basys3_Abacus_Top_drc_opted.rpt. Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' INFO: [Drc 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [Drc 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Placer Task INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs Phase 1 Placer Runtime Estimator Phase 1 Placer Runtime Estimator | Checksum: 18078c8d1 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.886 . Memory (MB): peak = 929.320 ; gain = 0.000 Phase 2 Placer Initialization Phase 2.1 Placer Initialization Core Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 929.320 ; gain = 0.000 Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 929.320 ; gain = 0.000 Phase 2.1.1 IO Placement/ Clock Placement/ Build Placer Device Phase 2.1.1.1 Pre-Place Cells Phase 2.1.1.1 Pre-Place Cells | Checksum: cb173ea3 Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 929.320 ; gain = 0.000 WARNING: [Place 30-568] A LUT 'u5/msg_array_reg[0]_LDC_i_1__0' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u5/msg_array_reg[0]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u5/msg_array_reg[1]_LDC_i_1__0' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u5/msg_array_reg[1]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u5/msg_array_reg[2]_LDC_i_1__0' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u5/msg_array_reg[2]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u5/msg_array_reg[3]_LDC_i_1__0' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u5/msg_array_reg[3]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u5/msg_array_reg[4]_LDC_i_1__0' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u5/msg_array_reg[4]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u5/msg_array_reg[5]_LDC_i_1__0' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u5/msg_array_reg[5]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u5/msg_array_reg[6]_LDC_i_1__0' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u5/msg_array_reg[6]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u5/msg_array_reg[7]_LDC_i_1__0' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u5/msg_array_reg[7]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u5/msg_array_reg[8]_LDC_i_1__0' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u5/msg_array_reg[8]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u5/msg_array_reg[9]_LDC_i_1__0' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u5/msg_array_reg[9]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u4/msg_array_reg[0]_LDC_i_1__1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u4/msg_array_reg[0]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u4/msg_array_reg[10]_LDC_i_1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u4/msg_array_reg[10]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u4/msg_array_reg[11]_LDC_i_1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u4/msg_array_reg[11]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u4/msg_array_reg[12]_LDC_i_1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u4/msg_array_reg[12]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u4/msg_array_reg[13]_LDC_i_1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u4/msg_array_reg[13]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u4/msg_array_reg[14]_LDC_i_1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u4/msg_array_reg[14]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u4/msg_array_reg[15]_LDC_i_1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u4/msg_array_reg[15]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u4/msg_array_reg[16]_LDC_i_1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u4/msg_array_reg[16]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u4/msg_array_reg[17]_LDC_i_1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u4/msg_array_reg[17]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u4/msg_array_reg[18]_LDC_i_1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u4/msg_array_reg[18]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u4/msg_array_reg[19]_LDC_i_1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u4/msg_array_reg[19]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u4/msg_array_reg[1]_LDC_i_1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u4/msg_array_reg[1]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u4/msg_array_reg[2]_LDC_i_1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u4/msg_array_reg[2]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u4/msg_array_reg[3]_LDC_i_1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u4/msg_array_reg[3]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u4/msg_array_reg[4]_LDC_i_1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u4/msg_array_reg[4]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u4/msg_array_reg[5]_LDC_i_1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u4/msg_array_reg[5]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u4/msg_array_reg[6]_LDC_i_1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u4/msg_array_reg[6]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u4/msg_array_reg[7]_LDC_i_1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u4/msg_array_reg[7]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u4/msg_array_reg[8]_LDC_i_1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u4/msg_array_reg[8]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u4/msg_array_reg[9]_LDC_i_1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u4/msg_array_reg[9]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u6/msg_array_reg[0]_LDC_i_1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u6/msg_array_reg[0]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u6/msg_array_reg[1]_LDC_i_1__1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u6/msg_array_reg[1]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u6/msg_array_reg[2]_LDC_i_1__1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u6/msg_array_reg[2]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u6/msg_array_reg[3]_LDC_i_1__1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u6/msg_array_reg[3]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u6/msg_array_reg[4]_LDC_i_1__1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u6/msg_array_reg[4]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u6/msg_array_reg[5]_LDC_i_1__1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u6/msg_array_reg[5]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u6/msg_array_reg[6]_LDC_i_1__1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u6/msg_array_reg[6]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u6/msg_array_reg[7]_LDC_i_1__1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u6/msg_array_reg[7]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u6/msg_array_reg[8]_LDC_i_1__1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u6/msg_array_reg[8]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'u6/msg_array_reg[9]_LDC_i_1__1' is driving clock pin of 1 registers. This could lead to large hold time violations. First few involved registers are: u6/msg_array_reg[9]_LDC {LDCE} WARNING: [Place 30-568] A LUT 'B1_reg[7]_i_1' is driving clock pin of 8 registers. This could lead to large hold time violations. First few involved registers are: B1_reg[6] {LDCE} B1_reg[5] {LDCE} B1_reg[4] {LDCE} B1_reg[3] {LDCE} B1_reg[2] {LDCE} WARNING: [Place 30-568] A LUT 'B2_reg[7]_i_1' is driving clock pin of 8 registers. This could lead to large hold time violations. First few involved registers are: B2_reg[1] {LDCE} B2_reg[0] {LDCE} B2_reg[2] {LDCE} B2_reg[3] {LDCE} B2_reg[4] {LDCE} WARNING: [Place 30-568] A LUT 'B_reg[15]_i_2' is driving clock pin of 16 registers. This could lead to large hold time violations. First few involved registers are: B_reg[0] {LDCE} B_reg[10] {LDCE} B_reg[11] {LDCE} B_reg[12] {LDCE} B_reg[13] {LDCE} INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 2.1.1.2 IO & Clk Clean Up Phase 2.1.1.2 IO & Clk Clean Up | Checksum: cb173ea3 Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 944.270 ; gain = 14.949 Phase 2.1.1.3 Implementation Feasibility check On IDelay Phase 2.1.1.3 Implementation Feasibility check On IDelay | Checksum: cb173ea3 Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 944.270 ; gain = 14.949 Phase 2.1.1.4 Commit IO Placement Phase 2.1.1.4 Commit IO Placement | Checksum: d0fa04ae Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 944.270 ; gain = 14.949 Phase 2.1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1112bddaf Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 944.270 ; gain = 14.949 Phase 2.1.2 Build Placer Netlist Model Phase 2.1.2.1 Place Init Design Phase 2.1.2.1 Place Init Design | Checksum: 2038d545a Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 944.270 ; gain = 14.949 Phase 2.1.2 Build Placer Netlist Model | Checksum: 2038d545a Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 944.270 ; gain = 14.949 Phase 2.1.3 Constrain Clocks/Macros Phase 2.1.3.1 Constrain Global/Regional Clocks Phase 2.1.3.1 Constrain Global/Regional Clocks | Checksum: 2038d545a Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 944.270 ; gain = 14.949 Phase 2.1.3 Constrain Clocks/Macros | Checksum: 2038d545a Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 944.270 ; gain = 14.949 Phase 2.1 Placer Initialization Core | Checksum: 2038d545a Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 944.270 ; gain = 14.949 Phase 2 Placer Initialization | Checksum: 2038d545a Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 944.270 ; gain = 14.949 Phase 3 Global Placement Phase 3 Global Placement | Checksum: 13074b208 Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 944.270 ; gain = 14.949 Phase 4 Detail Placement Phase 4.1 Commit Multi Column Macros Phase 4.1 Commit Multi Column Macros | Checksum: 13074b208 Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 944.270 ; gain = 14.949 Phase 4.2 Commit Most Macros & LUTRAMs Phase 4.2 Commit Most Macros & LUTRAMs | Checksum: 1edd9c422 Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 944.270 ; gain = 14.949 Phase 4.3 Area Swap Optimization Phase 4.3 Area Swap Optimization | Checksum: 12e190b3a Time (s): cpu = 00:00:03 ; elapsed = 00:00:06 . Memory (MB): peak = 944.270 ; gain = 14.949 Phase 4.4 Commit Small Macros & Core Logic Phase 4.4.1 Commit Slice Clusters Phase 4.4.1 Commit Slice Clusters | Checksum: 1d7010131 Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 944.270 ; gain = 14.949 Phase 4.4 Commit Small Macros & Core Logic | Checksum: 1d7010131 Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 944.270 ; gain = 14.949 Phase 4.5 Clock Restriction Legalization for Leaf Columns Phase 4.5 Clock Restriction Legalization for Leaf Columns | Checksum: 1d7010131 Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 944.270 ; gain = 14.949 Phase 4.6 Clock Restriction Legalization for Non-Clock Pins Phase 4.6 Clock Restriction Legalization for Non-Clock Pins | Checksum: 1d7010131 Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 944.270 ; gain = 14.949 Phase 4.7 Re-assign LUT pins Phase 4.7 Re-assign LUT pins | Checksum: 1d7010131 Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 944.270 ; gain = 14.949 Phase 4 Detail Placement | Checksum: 1d7010131 Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 944.270 ; gain = 14.949 Phase 5 Post Placement Optimization and Clean-Up Phase 5.1 PCOPT Shape updates Phase 5.1 PCOPT Shape updates | Checksum: 19f7c4e18 Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 944.270 ; gain = 14.949 Phase 5.2 Post Placement Cleanup Phase 5.2 Post Placement Cleanup | Checksum: 19f7c4e18 Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 944.270 ; gain = 14.949 Phase 5.3 Placer Reporting Phase 5.3 Placer Reporting | Checksum: 19f7c4e18 Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 944.270 ; gain = 14.949 Phase 5.4 Final Placement Cleanup Phase 5.4 Final Placement Cleanup | Checksum: 24d37e0d8 Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 944.270 ; gain = 14.949 Phase 5 Post Placement Optimization and Clean-Up | Checksum: 24d37e0d8 Time (s): cpu = 00:00:03 ; elapsed = 00:00:07 . Memory (MB): peak = 944.270 ; gain = 14.949 Ending Placer Task | Checksum: 172c6493c Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 944.270 ; gain = 14.949 INFO: [Common 17-83] Releasing license: Implementation 37 Infos, 43 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:04 ; elapsed = 00:00:09 . Memory (MB): peak = 944.270 ; gain = 14.949 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.342 . Memory (MB): peak = 944.270 ; gain = 0.000 report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.197 . Memory (MB): peak = 944.270 ; gain = 0.000 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' Running DRC as a precondition to command route_design INFO: [Drc 23-27] Running DRC with 2 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs Phase 1 Build RT Design Phase 1 Build RT Design | Checksum: 1656a49a1 Time (s): cpu = 00:00:31 ; elapsed = 00:00:29 . Memory (MB): peak = 1022.398 ; gain = 78.129 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Pre Route Cleanup Phase 2.1 Pre Route Cleanup | Checksum: 1656a49a1 Time (s): cpu = 00:00:31 ; elapsed = 00:00:30 . Memory (MB): peak = 1027.234 ; gain = 82.965 Number of Nodes with overlaps = 0 Phase 2 Router Initialization | Checksum: 16462ed07 Time (s): cpu = 00:00:31 ; elapsed = 00:00:30 . Memory (MB): peak = 1033.496 ; gain = 89.227 Phase 3 Initial Routing Phase 3 Initial Routing | Checksum: 80beadea Time (s): cpu = 00:00:32 ; elapsed = 00:00:30 . Memory (MB): peak = 1033.496 ; gain = 89.227 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 121 Number of Nodes with overlaps = 0 Phase 4.1 Global Iteration 0 | Checksum: 6354899e Time (s): cpu = 00:00:32 ; elapsed = 00:00:31 . Memory (MB): peak = 1033.496 ; gain = 89.227 Phase 4 Rip-up And Reroute | Checksum: 6354899e Time (s): cpu = 00:00:32 ; elapsed = 00:00:31 . Memory (MB): peak = 1033.496 ; gain = 89.227 Phase 5 Post Hold Fix Phase 5 Post Hold Fix | Checksum: 6354899e Time (s): cpu = 00:00:32 ; elapsed = 00:00:31 . Memory (MB): peak = 1033.496 ; gain = 89.227 Phase 6 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 0.193574 % Global Horizontal Routing Utilization = 0.251171 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Congestion Report North Dir 1x1 Area, Max Cong = 24.3243%, No Congested Regions. South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions. East Dir 1x1 Area, Max Cong = 38.2353%, No Congested Regions. West Dir 1x1 Area, Max Cong = 20.5882%, No Congested Regions. Phase 6 Route finalize | Checksum: 6354899e Time (s): cpu = 00:00:32 ; elapsed = 00:00:31 . Memory (MB): peak = 1033.496 ; gain = 89.227 Phase 7 Verifying routed nets Verification completed successfully Phase 7 Verifying routed nets | Checksum: 6354899e Time (s): cpu = 00:00:32 ; elapsed = 00:00:31 . Memory (MB): peak = 1033.496 ; gain = 89.227 Phase 8 Depositing Routes Phase 8 Depositing Routes | Checksum: 657f070d Time (s): cpu = 00:00:32 ; elapsed = 00:00:31 . Memory (MB): peak = 1033.496 ; gain = 89.227 INFO: [Route 35-16] Router Completed Successfully Routing Is Done. Time (s): cpu = 00:00:00 ; elapsed = 00:00:32 . Memory (MB): peak = 1033.496 ; gain = 89.227 INFO: [Common 17-83] Releasing license: Implementation 45 Infos, 43 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:33 . Memory (MB): peak = 1033.496 ; gain = 89.227 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.413 . Memory (MB): peak = 1033.496 ; gain = 0.000 INFO: [Drc 23-27] Running DRC with 2 threads INFO: [Coretcl 2-168] The results of DRC are in file C:/Users/Owner/Desktop/Verilog_Practice/project_1/project_1.runs/impl_1/Basys3_Abacus_Top_drc_routed.rpt. INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs WARNING: [Power 33-232] No user defined clocks was found in the design! Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t' Running DRC as a precondition to command write_bitstream INFO: [Drc 23-27] Running DRC with 2 threads ERROR: [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 1 out of 50 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk. ERROR: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 1 out of 50 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk. WARNING: [Drc 23-20] Rule violation (CFGBVS-1) Missing CFGBVS and CONFIG_VOLTAGE Design Properties - Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net n_0_B1_reg[7]_i_1 is a gated clock net sourced by a combinational pin B1_reg[7]_i_1/O, cell B1_reg[7]_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net n_0_B2_reg[7]_i_1 is a gated clock net sourced by a combinational pin B2_reg[7]_i_1/O, cell B2_reg[7]_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net n_0_B_reg[15]_i_2 is a gated clock net sourced by a combinational pin B_reg[15]_i_2/O, cell B_reg[15]_i_2. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u4/n_0_msg_array_reg[0]_LDC_i_1__1 is a gated clock net sourced by a combinational pin u4/msg_array_reg[0]_LDC_i_1__1/O, cell u4/msg_array_reg[0]_LDC_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u4/n_0_msg_array_reg[10]_LDC_i_1 is a gated clock net sourced by a combinational pin u4/msg_array_reg[10]_LDC_i_1/O, cell u4/msg_array_reg[10]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u4/n_0_msg_array_reg[11]_LDC_i_1 is a gated clock net sourced by a combinational pin u4/msg_array_reg[11]_LDC_i_1/O, cell u4/msg_array_reg[11]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u4/n_0_msg_array_reg[12]_LDC_i_1 is a gated clock net sourced by a combinational pin u4/msg_array_reg[12]_LDC_i_1/O, cell u4/msg_array_reg[12]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u4/n_0_msg_array_reg[13]_LDC_i_1 is a gated clock net sourced by a combinational pin u4/msg_array_reg[13]_LDC_i_1/O, cell u4/msg_array_reg[13]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u4/n_0_msg_array_reg[14]_LDC_i_1 is a gated clock net sourced by a combinational pin u4/msg_array_reg[14]_LDC_i_1/O, cell u4/msg_array_reg[14]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u4/n_0_msg_array_reg[15]_LDC_i_1 is a gated clock net sourced by a combinational pin u4/msg_array_reg[15]_LDC_i_1/O, cell u4/msg_array_reg[15]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u4/n_0_msg_array_reg[16]_LDC_i_1 is a gated clock net sourced by a combinational pin u4/msg_array_reg[16]_LDC_i_1/O, cell u4/msg_array_reg[16]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u4/n_0_msg_array_reg[17]_LDC_i_1 is a gated clock net sourced by a combinational pin u4/msg_array_reg[17]_LDC_i_1/O, cell u4/msg_array_reg[17]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u4/n_0_msg_array_reg[18]_LDC_i_1 is a gated clock net sourced by a combinational pin u4/msg_array_reg[18]_LDC_i_1/O, cell u4/msg_array_reg[18]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u4/n_0_msg_array_reg[19]_LDC_i_1 is a gated clock net sourced by a combinational pin u4/msg_array_reg[19]_LDC_i_1/O, cell u4/msg_array_reg[19]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u4/n_0_msg_array_reg[1]_LDC_i_1 is a gated clock net sourced by a combinational pin u4/msg_array_reg[1]_LDC_i_1/O, cell u4/msg_array_reg[1]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u4/n_0_msg_array_reg[2]_LDC_i_1 is a gated clock net sourced by a combinational pin u4/msg_array_reg[2]_LDC_i_1/O, cell u4/msg_array_reg[2]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u4/n_0_msg_array_reg[3]_LDC_i_1 is a gated clock net sourced by a combinational pin u4/msg_array_reg[3]_LDC_i_1/O, cell u4/msg_array_reg[3]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u4/n_0_msg_array_reg[4]_LDC_i_1 is a gated clock net sourced by a combinational pin u4/msg_array_reg[4]_LDC_i_1/O, cell u4/msg_array_reg[4]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u4/n_0_msg_array_reg[5]_LDC_i_1 is a gated clock net sourced by a combinational pin u4/msg_array_reg[5]_LDC_i_1/O, cell u4/msg_array_reg[5]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u4/n_0_msg_array_reg[6]_LDC_i_1 is a gated clock net sourced by a combinational pin u4/msg_array_reg[6]_LDC_i_1/O, cell u4/msg_array_reg[6]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u4/n_0_msg_array_reg[7]_LDC_i_1 is a gated clock net sourced by a combinational pin u4/msg_array_reg[7]_LDC_i_1/O, cell u4/msg_array_reg[7]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u4/n_0_msg_array_reg[8]_LDC_i_1 is a gated clock net sourced by a combinational pin u4/msg_array_reg[8]_LDC_i_1/O, cell u4/msg_array_reg[8]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u4/n_0_msg_array_reg[9]_LDC_i_1 is a gated clock net sourced by a combinational pin u4/msg_array_reg[9]_LDC_i_1/O, cell u4/msg_array_reg[9]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u5/n_0_msg_array_reg[0]_LDC_i_1__0 is a gated clock net sourced by a combinational pin u5/msg_array_reg[0]_LDC_i_1__0/O, cell u5/msg_array_reg[0]_LDC_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u5/n_0_msg_array_reg[1]_LDC_i_1__0 is a gated clock net sourced by a combinational pin u5/msg_array_reg[1]_LDC_i_1__0/O, cell u5/msg_array_reg[1]_LDC_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u5/n_0_msg_array_reg[2]_LDC_i_1__0 is a gated clock net sourced by a combinational pin u5/msg_array_reg[2]_LDC_i_1__0/O, cell u5/msg_array_reg[2]_LDC_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u5/n_0_msg_array_reg[3]_LDC_i_1__0 is a gated clock net sourced by a combinational pin u5/msg_array_reg[3]_LDC_i_1__0/O, cell u5/msg_array_reg[3]_LDC_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u5/n_0_msg_array_reg[4]_LDC_i_1__0 is a gated clock net sourced by a combinational pin u5/msg_array_reg[4]_LDC_i_1__0/O, cell u5/msg_array_reg[4]_LDC_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u5/n_0_msg_array_reg[5]_LDC_i_1__0 is a gated clock net sourced by a combinational pin u5/msg_array_reg[5]_LDC_i_1__0/O, cell u5/msg_array_reg[5]_LDC_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u5/n_0_msg_array_reg[6]_LDC_i_1__0 is a gated clock net sourced by a combinational pin u5/msg_array_reg[6]_LDC_i_1__0/O, cell u5/msg_array_reg[6]_LDC_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u5/n_0_msg_array_reg[7]_LDC_i_1__0 is a gated clock net sourced by a combinational pin u5/msg_array_reg[7]_LDC_i_1__0/O, cell u5/msg_array_reg[7]_LDC_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u5/n_0_msg_array_reg[8]_LDC_i_1__0 is a gated clock net sourced by a combinational pin u5/msg_array_reg[8]_LDC_i_1__0/O, cell u5/msg_array_reg[8]_LDC_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u5/n_0_msg_array_reg[9]_LDC_i_1__0 is a gated clock net sourced by a combinational pin u5/msg_array_reg[9]_LDC_i_1__0/O, cell u5/msg_array_reg[9]_LDC_i_1__0. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u6/n_0_msg_array_reg[0]_LDC_i_1 is a gated clock net sourced by a combinational pin u6/msg_array_reg[0]_LDC_i_1/O, cell u6/msg_array_reg[0]_LDC_i_1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u6/n_0_msg_array_reg[1]_LDC_i_1__1 is a gated clock net sourced by a combinational pin u6/msg_array_reg[1]_LDC_i_1__1/O, cell u6/msg_array_reg[1]_LDC_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u6/n_0_msg_array_reg[2]_LDC_i_1__1 is a gated clock net sourced by a combinational pin u6/msg_array_reg[2]_LDC_i_1__1/O, cell u6/msg_array_reg[2]_LDC_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u6/n_0_msg_array_reg[3]_LDC_i_1__1 is a gated clock net sourced by a combinational pin u6/msg_array_reg[3]_LDC_i_1__1/O, cell u6/msg_array_reg[3]_LDC_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u6/n_0_msg_array_reg[4]_LDC_i_1__1 is a gated clock net sourced by a combinational pin u6/msg_array_reg[4]_LDC_i_1__1/O, cell u6/msg_array_reg[4]_LDC_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u6/n_0_msg_array_reg[5]_LDC_i_1__1 is a gated clock net sourced by a combinational pin u6/msg_array_reg[5]_LDC_i_1__1/O, cell u6/msg_array_reg[5]_LDC_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u6/n_0_msg_array_reg[6]_LDC_i_1__1 is a gated clock net sourced by a combinational pin u6/msg_array_reg[6]_LDC_i_1__1/O, cell u6/msg_array_reg[6]_LDC_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u6/n_0_msg_array_reg[7]_LDC_i_1__1 is a gated clock net sourced by a combinational pin u6/msg_array_reg[7]_LDC_i_1__1/O, cell u6/msg_array_reg[7]_LDC_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u6/n_0_msg_array_reg[8]_LDC_i_1__1 is a gated clock net sourced by a combinational pin u6/msg_array_reg[8]_LDC_i_1__1/O, cell u6/msg_array_reg[8]_LDC_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PDRC-153) Gated clock check - Net u6/n_0_msg_array_reg[9]_LDC_i_1__1 is a gated clock net sourced by a combinational pin u6/msg_array_reg[9]_LDC_i_1__1/O, cell u6/msg_array_reg[9]_LDC_i_1__1. This is not good design practice and will likely impact performance. For SLICE registers, for example, use the CE pin to control the loading of data. WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT B1_reg[7]_i_1 is driving clock pin of 8 cells. This could lead to large hold time violations. First few involved cells are: B1_reg[6] {LDCE} B1_reg[5] {LDCE} B1_reg[4] {LDCE} B1_reg[3] {LDCE} B1_reg[2] {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT B2_reg[7]_i_1 is driving clock pin of 8 cells. This could lead to large hold time violations. First few involved cells are: B2_reg[1] {LDCE} B2_reg[0] {LDCE} B2_reg[2] {LDCE} B2_reg[3] {LDCE} B2_reg[4] {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT B_reg[15]_i_2 is driving clock pin of 16 cells. This could lead to large hold time violations. First few involved cells are: B_reg[0] {LDCE} B_reg[10] {LDCE} B_reg[11] {LDCE} B_reg[12] {LDCE} B_reg[13] {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u4/msg_array_reg[0]_LDC_i_1__1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u4/msg_array_reg[0]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u4/msg_array_reg[10]_LDC_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u4/msg_array_reg[10]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u4/msg_array_reg[11]_LDC_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u4/msg_array_reg[11]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u4/msg_array_reg[12]_LDC_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u4/msg_array_reg[12]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u4/msg_array_reg[13]_LDC_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u4/msg_array_reg[13]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u4/msg_array_reg[14]_LDC_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u4/msg_array_reg[14]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u4/msg_array_reg[15]_LDC_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u4/msg_array_reg[15]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u4/msg_array_reg[16]_LDC_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u4/msg_array_reg[16]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u4/msg_array_reg[17]_LDC_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u4/msg_array_reg[17]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u4/msg_array_reg[18]_LDC_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u4/msg_array_reg[18]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u4/msg_array_reg[19]_LDC_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u4/msg_array_reg[19]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u4/msg_array_reg[1]_LDC_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u4/msg_array_reg[1]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u4/msg_array_reg[2]_LDC_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u4/msg_array_reg[2]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u4/msg_array_reg[3]_LDC_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u4/msg_array_reg[3]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u4/msg_array_reg[4]_LDC_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u4/msg_array_reg[4]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u4/msg_array_reg[5]_LDC_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u4/msg_array_reg[5]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u4/msg_array_reg[6]_LDC_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u4/msg_array_reg[6]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u4/msg_array_reg[7]_LDC_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u4/msg_array_reg[7]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u4/msg_array_reg[8]_LDC_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u4/msg_array_reg[8]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u4/msg_array_reg[9]_LDC_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u4/msg_array_reg[9]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u5/msg_array_reg[0]_LDC_i_1__0 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u5/msg_array_reg[0]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u5/msg_array_reg[1]_LDC_i_1__0 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u5/msg_array_reg[1]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u5/msg_array_reg[2]_LDC_i_1__0 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u5/msg_array_reg[2]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u5/msg_array_reg[3]_LDC_i_1__0 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u5/msg_array_reg[3]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u5/msg_array_reg[4]_LDC_i_1__0 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u5/msg_array_reg[4]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u5/msg_array_reg[5]_LDC_i_1__0 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u5/msg_array_reg[5]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u5/msg_array_reg[6]_LDC_i_1__0 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u5/msg_array_reg[6]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u5/msg_array_reg[7]_LDC_i_1__0 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u5/msg_array_reg[7]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u5/msg_array_reg[8]_LDC_i_1__0 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u5/msg_array_reg[8]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u5/msg_array_reg[9]_LDC_i_1__0 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u5/msg_array_reg[9]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u6/msg_array_reg[0]_LDC_i_1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u6/msg_array_reg[0]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u6/msg_array_reg[1]_LDC_i_1__1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u6/msg_array_reg[1]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u6/msg_array_reg[2]_LDC_i_1__1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u6/msg_array_reg[2]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u6/msg_array_reg[3]_LDC_i_1__1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u6/msg_array_reg[3]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u6/msg_array_reg[4]_LDC_i_1__1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u6/msg_array_reg[4]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u6/msg_array_reg[5]_LDC_i_1__1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u6/msg_array_reg[5]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u6/msg_array_reg[6]_LDC_i_1__1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u6/msg_array_reg[6]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u6/msg_array_reg[7]_LDC_i_1__1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u6/msg_array_reg[7]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u6/msg_array_reg[8]_LDC_i_1__1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u6/msg_array_reg[8]_LDC {LDCE} WARNING: [Drc 23-20] Rule violation (PLHOLDVIO-2) Non-Optimal connections which could lead to hold violations - A LUT u6/msg_array_reg[9]_LDC_i_1__1 is driving clock pin of 1 cells. This could lead to large hold time violations. First few involved cells are: u6/msg_array_reg[9]_LDC {LDCE} INFO: [Vivado 12-3199] DRC finished with 2 Errors, 87 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run. INFO: [Common 17-83] Releasing license: Implementation ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors. while executing "write_bitstream -force Basys3_Abacus_Top.bit -bin_file" INFO: [Common 17-206] Exiting Vivado at Thu Nov 20 18:51:21 2014...