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Controlling output voltages on PmodDA4 from Basys2



I found similar question “Working with DA4 PMOD on Nexys 4” posted on 23 Oct. 2014 and answer from JColvin. I understand the hint about usage of internal voltage. Nevertheless I don’t see output voltages. It is not easy to me to follow applied code, because I have learned so far Verilog and example is given in VHDL.   

I am electrical engineer and programmer by education, but I am new to digital electronics and FPGAs. I have acquired some initial experience by learning book “Digital Design Using Digilent FPGA Boards. Verilog/ Active –HDL Edition” by Richard E.Haskell and Darrin M.Hanna from 2012. I have implemented many examples from the book on BASYS2 board that I have.

Now I would like to see voltages on outputs of PmodDA4 that I connect to my BASYS2 board. For beginning I will be satisfied with direct (permanent) voltages. I have been trying few versions of code and didn’t succeed.

Please, advise – what is wrong? May be many things…

I will try to describe my logic in details and attach my code too.    

I use Verilog. I connect PmodDA4 to JA connector of BASYS2 board.

I have to create 3 correct signals: SYNC, DIN and SCLK.

According to documentation I assume that:

1. SYNC: JA1 (B2) – pio<72> in ucf file.

2. DIN: JA2 (A3) – pio<73> in ucf file.

3. SCLK: JA4 (B5) – pio<75> in ucf file.

Default frequency of a board is 50 MHz. I use half of this frequency – 25 MHz as a SCLK signal.

I understand logic of operation so: if SYNC is high – data from signal DIN does not go into internal register of PmodDA4.

After SYNC went low – data starts to go into internal register of PmodDA4. It goes into PmodDA4 on each negedge of SCLK and it counted by PmodDA4. By data we mean signal DIN: 0 or 1. After transferring 32 bits into internal register of PmodDA4 we have to change SYNC on high. May be that not necessarily to do right away after 32 accumulated bits, but I do that in my code, because in any way we must bring SYNC high for min 15 ns and after low for initiation of a new cycle of writing data into internal register of PmodDA4.  I control that process by variable count.

I simulated the process with Aldec simulator and visually it seems to me correct. I assume that bit db31 on a page 7 of http://www.analog.com/media/en/technical-documentation/data-sheets/AD5628_5648_5668.pdf is a first bit in time among 32 bits that is clocked into internal register of PmodDA4.    

Here is a sequence of 32 bits that I try to produce, taking JColvin’s notice about using Internal source of power.

Don’t care bits db31, 30, 29, 28: 0000.

Command bits db27, 26, 25, 24: 1011.   

Address bits db23, 22, 21, 20: 1111 – command for having voltage on all 8 outputs.

For AD5628 12 bits db19, 18, 17, 16, 15, 14, 13, 12, 11, 10, 9, 8 equal to 1 for max output voltage: 111111111111.

And last 8 bits db7, 6, 5, 4, 3, 2, 1, 0: 00000001.

As I understood your notice bits db27 and db0 have to be 1 – for using internal voltage as a source.  

My code for the project is attached in file Basys2_PmodDA4_code.txt.


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