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GregyPooh

[nexys 3] How To Create Abnormal Clock Frequency?

Question

I am using the Nexys 3 board alongside the PmodI2S - Stereo Audio Output. 

 

After reading the data sheet for this PMOD, 
http://www.cirrus.com/en/pubs/proDatasheet/CS4344-45-48_F2.pdf (see Table 1 on pg.12)

it seems as though I have to create an abnormal clock frequency. 
And by abnormal I mean a clock that cannot be created using a clock divider.

For example, table 1 in the data sheet suggests that I use a master clock of 22.5792MHz, but there is no such whole number (call it X) where the Nexys system clock: 100MHz/X = 22.5792MHz. 

So, what are my options?

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Hi,

 

As far as I know you have only one option. You have to implement a ip core called "Clocking Wizard" which can be found in the ip catalog. From there you can chose either to instantiate a mmcm or a pll and generate a specific clock. For further information I would strongly recommend to search for the clocking wizard product guide and read it.

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Taking note that a cheap xtal is about 50 parts per million, so anything that gives 22.579,200 +/- 1,128.96 Hz (22,578,071 Hz to 22,580,328 Hz) should be 'close enough' to spec that nobody can tell (it makes the difference of 0.2s after playing audio for an hour...).
 
Options
 
a ) Use the clocking wizard to generate a PLL and end up with 22.580,645 MHz (0.23s of error after an hour)
 
b ) Use a PLL Primative, with multiply 7, divide 31 and end up with 22.580,645 MHz (once again, 0.23s of error after an hour)
 
c ) Use one PLL set to multiply 9, divide 35 to give 25.714,285MHz, and feed that through a second PLL at multply 36, divide 41 to get 22.578,397 MHz (0.13s out after an hour)
 
d ) Use three PLLs, multiply 8 divide 25, multiply 21 divide 25, multiply 21 divide 25 to get 22.579,200 MHz - bang on (however I don't think that Nexys3 has enough clock management tiles for this...)
 
e ) Exotic stuff - perhaps use a polyphase filter to resample the 448100 sample stream to different sample rate, perhaps 25MHz / 512 = 48.828,125 samples per second, then use a 25MHz I2S clock, which should at worst add 1 least significant bit of noise  - but why would you bother?
 
f ) Add an external clock source that is a more friendly frequency.
 
If I ever need to do anything tricky with clocking, I find it better to use clock management primitives than to use the Clocking Wizard, as you get exactly what you ask for. Once you've done it once it is a lot quicker too!

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You are right Hamster.... generally speaking for an user who is familiar with PLLs it is better use HDL primitives, it gives you more control over the code you are writing and it is easier to port from one project to another, provided you use the same FPGA. As far as I remember different FPGAs have different primitive functional models which makes it a bit confusing for somebody who is not familiar with this.

 

The main reason for suggesting the clocking wizard was that, for somebody who is new to Digital Clock Managers in a FPGA it is easier to have a graphical user interface in which you just add the input frequency and the desired output frequency and not worry about adding output buffers and calculating the exact multiplication and division factor; this is done automatically by the wizard. It's also easier when you port your project to a different FPGA because the clocking wizard is not specific to a particular FPGA. Never the less, and I may be wrong here, it's less optimized then using HDL primitives.

 

I would not by an external oscillator for this ... except if you want your project to be extremely precise. As Hamster said it shouldn't make much of a difference if its off by an approx of  0.02 MHz, it is a great opportunity to learn about clocking in a FPGA and it will cost you some time to learn it but it could save you a lot of time and money on the long run rather then always buying a oscillator when you are using an FPGA.

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Here's what I have done so far:

 

I tried out hamster's "exotic" approach. I used a 25MHz master clock, a sample rate of 25Mhz/512 = 48,828.125, and a "SCLK" frequency of 32 * sample rate. These were easy to create in Verilog using a clock divider.

 

I attempted to produce a 12kHz square wave using these clocks...

My test-bench gives me predictable results, but I do not get sound.

Now, I do not know if this is a clock issue or a PMOD issue. Either way I am doing something incorrectly here.

 

I'm hoping someone can hold my hand a little further to get this PMOD to work...

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What values are you sending to the DAC? All ones and all zero?

Been there done that..... A square wave of 0000 and FFFF (0 and -1) is quite quiet. Try 0x4000 and 0xC000. It will be at 50% regardless of any signed/unsigned issues.

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