it seems as though I have to create an abnormal clock frequency.
And by abnormal I mean a clock that cannot be created using a clock divider.
For example, table 1 in the data sheet suggests that I use a master clock of 22.5792MHz, but there is no such whole number (call it X) where the Nexys system clock: 100MHz/X = 22.5792MHz.
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GregyPooh
I am using the Nexys 3 board alongside the PmodI2S - Stereo Audio Output.
After reading the data sheet for this PMOD,
http://www.cirrus.com/en/pubs/proDatasheet/CS4344-45-48_F2.pdf (see Table 1 on pg.12)
it seems as though I have to create an abnormal clock frequency.
And by abnormal I mean a clock that cannot be created using a clock divider.
For example, table 1 in the data sheet suggests that I use a master clock of 22.5792MHz, but there is no such whole number (call it X) where the Nexys system clock: 100MHz/X = 22.5792MHz.
So, what are my options?
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