fpga problème hdmi_out sur fpga arty z7-20

[zazou]

Bonjour, 

je travail cette période sur le hdmi_out de la carte fpga arty z7-20, et comme tout le monde j'ai commencé par télécharger le fichier tuto de .git, deja apres l'implémentation y a rien qui s'affiche sur le deuxieme écran donc j'ai essayé de modifier les blocs IP par l'ajout d'un bloc qui convertit une image à une matrice et le lié avec le reste des blocs en appliquant les modifications nécessaires sur le BD et le .vhd , 

finalement, j'ai obtenue cette erreur.

Remarque à savoir : j'ai vérifié les liaisons en RTL design et elles me paraits correctes 

MErci pour vos aides, 

 

translated by google translate by JPEYRON

Hello,

I work this period on the hdmi_out of the art7 zp-20 fpga card, and like everyone else I started by downloading the .git tutorial file, already after the implementation there is nothing that appears on the second screen so I tried to modify the IP blocks by adding a block that converts an image to a matrix and binds it with the rest of the blocks by applying the necessary modifications on the BD and the .vhd,

finally, I got this error.

 

Note: I checked the links in RTL design and they seem correct to me

MErci for your help,

[jpeyron]

Hi @zazou,

Are you using Vivado 2016.4 ? The version of vivado does make a difference with vivado projects. If you are using a newer version of Vivado i would suggest to start with a fresh project. Load into vivado, upgrade/generate the ip cores(tools->reports->report ip status), create a wrapper and generate a bitstream. You might need to change a few of the xdc names due to an upgrade with the dvi2rgb and rgb2dvi ip cores.

thank you,

Jon

[zazou]

Hi @jpeyron

Merci pour votre réponse rapide, je suis déja passée par ces étapes, et du coup je comprends pas comment je peux placer Les pins SCL,SDA sachant qu'ils prennent M17 et M18 .

 

Merci encore une fois,

 

translated text using google translate by JPEYRON,

 

Thank you for your quick response, I have already gone through these steps, and suddenly I do not understand how I can place SCL pins, SDA knowing that they take M17 and M18.

 

Thanks again,

[jpeyron]

Hi @zazou,

Can you attach a copy of your wrapper, xdc and a screen shot of your block design.

thank you,

Jon

[zazou]

Hi @jpeyron

thanks for tour replay, 

• this is a copy of wrapper file :

--Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2017.4 (win64) Build 2086221 Fri Dec 15 20:55:39 MST 2017
--Date        : Fri May  4 12:45:45 2018
--Host        : DESKTOP-132D4SR running 64-bit major release  (build 9200)
--Command     : generate_target hdmi_out_wrapper.bd
--Design      : hdmi_out_wrapper
--Purpose     : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity hdmi_out_wrapper is
  port (
    DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
    DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
    DDR_cas_n : inout STD_LOGIC;
    DDR_ck_n : inout STD_LOGIC;
    DDR_ck_p : inout STD_LOGIC;
    DDR_cke : inout STD_LOGIC;
    DDR_cs_n : inout STD_LOGIC;
    DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
    DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    DDR_odt : inout STD_LOGIC;
    DDR_ras_n : inout STD_LOGIC;
    DDR_reset_n : inout STD_LOGIC;
    DDR_we_n : inout STD_LOGIC;
    FIXED_IO_ddr_vrn : inout STD_LOGIC;
    FIXED_IO_ddr_vrp : inout STD_LOGIC;
    FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
    FIXED_IO_ps_clk : inout STD_LOGIC;
    FIXED_IO_ps_porb : inout STD_LOGIC;
    FIXED_IO_ps_srstb : inout STD_LOGIC;
    HDMI_DDC_scl_io : inout STD_LOGIC;
    HDMI_DDC_sda_io : inout STD_LOGIC;
    HDMI_HPD_tri_i : in STD_LOGIC_VECTOR ( 0 to 0 );
    TMDS_clk_n : out STD_LOGIC;
    TMDS_clk_p : out STD_LOGIC;
    TMDS_data_n : out STD_LOGIC_VECTOR ( 2 downto 0 );
    TMDS_data_p : out STD_LOGIC_VECTOR ( 2 downto 0 )
  );
end hdmi_out_wrapper;

architecture STRUCTURE of hdmi_out_wrapper is
  component hdmi_out is
  port (
    DDR_cas_n : inout STD_LOGIC;
    DDR_cke : inout STD_LOGIC;
    DDR_ck_n : inout STD_LOGIC;
    DDR_ck_p : inout STD_LOGIC;
    DDR_cs_n : inout STD_LOGIC;
    DDR_reset_n : inout STD_LOGIC;
    DDR_odt : inout STD_LOGIC;
    DDR_ras_n : inout STD_LOGIC;
    DDR_we_n : inout STD_LOGIC;
    DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
    DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
    DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
    DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
    FIXED_IO_ddr_vrn : inout STD_LOGIC;
    FIXED_IO_ddr_vrp : inout STD_LOGIC;
    FIXED_IO_ps_srstb : inout STD_LOGIC;
    FIXED_IO_ps_clk : inout STD_LOGIC;
    FIXED_IO_ps_porb : inout STD_LOGIC;
    HDMI_DDC_sda_i : in STD_LOGIC;
    HDMI_DDC_sda_o : out STD_LOGIC;
    HDMI_DDC_sda_t : out STD_LOGIC;
    HDMI_DDC_scl_i : in STD_LOGIC;
    HDMI_DDC_scl_o : out STD_LOGIC;
    HDMI_DDC_scl_t : out STD_LOGIC;
    HDMI_HPD_tri_i : in STD_LOGIC_VECTOR ( 0 to 0 );
    TMDS_clk_p : out STD_LOGIC;
    TMDS_clk_n : out STD_LOGIC;
    TMDS_data_p : out STD_LOGIC_VECTOR ( 2 downto 0 );
    TMDS_data_n : out STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  end component hdmi_out;
  component IOBUF is
  port (
    I : in STD_LOGIC;
    O : out STD_LOGIC;
    T : in STD_LOGIC;
    IO : inout STD_LOGIC
  );
  end component IOBUF;
  signal HDMI_DDC_scl_i : STD_LOGIC;
  signal HDMI_DDC_scl_o : STD_LOGIC;
  signal HDMI_DDC_scl_t : STD_LOGIC;
  signal HDMI_DDC_sda_i : STD_LOGIC;
  signal HDMI_DDC_sda_o : STD_LOGIC;
  signal HDMI_DDC_sda_t : STD_LOGIC;
begin
HDMI_DDC_scl_iobuf: component IOBUF
     port map (
      I => HDMI_DDC_scl_o,
      IO => HDMI_DDC_scl_io,
      O => HDMI_DDC_scl_i,
      T => HDMI_DDC_scl_t
    );
HDMI_DDC_sda_iobuf: component IOBUF
     port map (
      I => HDMI_DDC_sda_o,
      IO => HDMI_DDC_sda_io,
      O => HDMI_DDC_sda_i,
      T => HDMI_DDC_sda_t
    );
hdmi_out_i: component hdmi_out
     port map (
      DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
      DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
      DDR_cas_n => DDR_cas_n,
      DDR_ck_n => DDR_ck_n,
      DDR_ck_p => DDR_ck_p,
      DDR_cke => DDR_cke,
      DDR_cs_n => DDR_cs_n,
      DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
      DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
      DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
      DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
      DDR_odt => DDR_odt,
      DDR_ras_n => DDR_ras_n,
      DDR_reset_n => DDR_reset_n,
      DDR_we_n => DDR_we_n,
      FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
      FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
      FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
      FIXED_IO_ps_clk => FIXED_IO_ps_clk,
      FIXED_IO_ps_porb => FIXED_IO_ps_porb,
      FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
      HDMI_DDC_scl_i => HDMI_DDC_scl_i,
      HDMI_DDC_scl_o => HDMI_DDC_scl_o,
      HDMI_DDC_scl_t => HDMI_DDC_scl_t,
      HDMI_DDC_sda_i => HDMI_DDC_sda_i,
      HDMI_DDC_sda_o => HDMI_DDC_sda_o,
      HDMI_DDC_sda_t => HDMI_DDC_sda_t,
      HDMI_HPD_tri_i(0) => HDMI_HPD_tri_i(0),
      TMDS_clk_n => TMDS_clk_n,
      TMDS_clk_p => TMDS_clk_p,
      TMDS_data_n(2 downto 0) => TMDS_data_n(2 downto 0),
      TMDS_data_p(2 downto 0) => TMDS_data_p(2 downto 0)
    );
end STRUCTURE;
 

 

• and this the XDC 

set_property -dict {PACKAGE_PIN L17 IOSTANDARD TMDS_33} [get_ports TMDS_clk_n]
set_property -dict {PACKAGE_PIN L16 IOSTANDARD TMDS_33} [get_ports TMDS_clk_p]

set_property IOSTANDARD TMDS_33 [get_ports {TMDS_data_n[0]}]
set_property PACKAGE_PIN K18 [get_ports {TMDS_data_n[0]}]

set_property PACKAGE_PIN K17 [get_ports {TMDS_data_p[0]}]
set_property IOSTANDARD TMDS_33 [get_ports {TMDS_data_p[0]}]

set_property IOSTANDARD TMDS_33 [get_ports {TMDS_data_n[1]}]
set_property PACKAGE_PIN J19 [get_ports {TMDS_data_n[1]}]

set_property PACKAGE_PIN K19 [get_ports {TMDS_data_p[1]}]
set_property IOSTANDARD TMDS_33 [get_ports {TMDS_data_p[1]}]

set_property IOSTANDARD TMDS_33 [get_ports {TMDS_data_n[2]}]
set_property PACKAGE_PIN H18 [get_ports {TMDS_data_n[2]}]

set_property PACKAGE_PIN J18 [get_ports {TMDS_data_p[2]}]
set_property IOSTANDARD TMDS_33 [get_ports {TMDS_data_p[2]}]

set_property PACKAGE_PIN R19 [get_ports {hdmi_hpd_tri_i[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {hdmi_hpd_tri_i[0]}]

set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports hdmi_ddc_scl_io]
set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports hdmi_ddc_sda_io]
 

 

 

• and this the BD :

 

 

NB : je travaille sur la version vivado 2017.4 , j'ai télecharger le fichier <hdmi_out> du .git et j'ai ajouter le bloc file_im pour convertir une image .JPEG en matrice XY 

translated with google translate by JPEYRON

NB: I am working on the version vivado 2017.4, I downloaded the file <hdmi_out> of .git and I add the block file_im to convert a picture .JPEG XY matrix

 

thanks for your Help !

Best regards 

[jpeyron]

Hi @zazou,

First thing i see is the xdc needs match the wrapper pin names. I.E.

set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports hdmi_ddc_scl_io]
set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports hdmi_ddc_sda_io]

should be 

set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS33} [get_ports HDMI_DDC_scl_io]
set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports  HDMI_DDC_sda_io]

 

thank you,

Jon

[zazou]

HI @jpeyron

I changed the XDC pin names as you said to me, but i have always the same error, 

 

[jpeyron]

Hi @zazou,

Here is a xilinx AR document that seems very similar to your issue. I would try the "set_property DONT_TOUCH true [get_cells <lut5_name>]"

thank you,

Jon 

[zazou]

hello @jpeyron

thank you for your reply,
I do not understand why the card does not send anything via the HDMI_OUT port, even if I followed the demonstration found on the GitHub https://github.com/Digilent/Arty-Z7-20-hdmi-out and I tried it with the Vivado 2017.4, Vivado 2016.4 and the SDK 2016.4, everything compiles but nothing that is displayed!
I am stuck !

 

[jpeyron]

Hi @zazou,

what Os are you using? I would stick with Vivado 2016.4 since this is the version it was made for and should not require any changes beside potentially the xdc discussed above. Can you attach a picture of your set up? Have you checked to make sure the HDMI in and HDMI out are connected correctly? Are you changing anything in the project? Have you tried using a fresh untouched project and starting over?

thank you,

Jon

[zazou]

Hi @jpeyron

j'ai finalement réussi à faire marché le port HDMI_Out de ma carte, et là il me reste que modifier les blocs pour mémoriser des images et les envoyer en sortie, 

avez-vous une idée comment le faire ? 

je vous remercie,

 

<Translation added by JColvin>

Hi @jpeyron

I finally managed to market the HDMI_Out port of my card, and here I still have to modify the blocks to memorize images and send them out,

do you have an idea how to do it?

Thank you,

[jpeyron]

Hi @zazou,

To clarify you are talking about still images? I reached out to a co-worker and they suggested that you can use one of the functions that copies data from one frame buffer to another as a reference. The Genesys 2 OOB demo displays an image loaded from flash memory (and has another sdk app which loads an image into flash), so that is probably another good reference. Also gimp can be used to export an image to a C header, so that's a pretty good way to get images into the app to start working with them. Fundamentally, with the hardware set up, all that is required is to iterate across two arrays, and copy pixel data from the source to the destination. The Genesys 2 might just use memcpy, I don't quite remember, which won't work with Gimp headers, but the video in to video out rescale function shows how to iterate across the destination memory, and the flash loader shows how to iterate across the source memory..

thank you,

Jon

 

[zazou]

salut @jpeyron

Je vous remerci pour votre réponse,

Donc si j'ai bien compris, modifier les blocs du fichier demo HDMI_OUT de la carte Arty z7-20 ce n'est pas une bonne idée !! et il faut utiliser le SDK pour exporter l'image ? 

Mais comment utiliser le Gimp avec le FPGA ? est-ce-qu'il y a un tutoriel ou des documents ??

merci en avance 

<translation by JColvin via Google Translate>

hi @jpeyron

I thank you for your answer,

So if I understand correctly, to modify the blocks of the file demo HDMI_OUT of the card Arty z7-20 it is not a good idea !! and you have to use the SDK to export the image?

But how to use Gimp with the FPGA? is there a tutorial or documents?

thank you in advance

[jpeyron]

Hi @zazou,

We are suggesting that you look at the genesys 2's oob demo as a reference for how to alter the hdmi-out for the arty-z7-20. We do not have a tutorial or documentation on how to do use Gimp.  I did find a project that uses Gimp here but I am not sure it will be helpful for your project.

thank you,

Jon