I am back to working with customizing the rgb2dvi IP. As mentioned in an earlier post, I made the changes in .vhd files, and I set the compile order of the .xdc files. I wrote a simple video generator (which also outputs the appropriate timing signals to the IP) in verilog, and a 'top' module that connects the two together. The design needs an external clock, which I will supply and I found which pin I need to use to get a universal clock.
I have two questions:
1) The IP as a asynchronous reset, and the documentation says 'Asynchronous reset of configurable polarity. Assert, if PixelClk and SerialClk are not within spec.'. The comment next to the source code itself says 'asynchronous reset; must be reset when RefClk is not within spec'. Can someone explain exactly what this means in simple English? I could not find any signal called 'RefClk' in the design. Practically, what should I do with the reset?
2) I attached a picture of the synthesis schematic from Vivado. Now, my video generator has a video data output of 24 bits (3 8 bit RGB values), and the IP has a video data input of 24 bits. So what are the D and Q signals coming out of the video generator, and why are they 2 bits each?
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dgottesm
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I am back to working with customizing the rgb2dvi IP. As mentioned in an earlier post, I made the changes in .vhd files, and I set the compile order of the .xdc files. I wrote a simple video generator (which also outputs the appropriate timing signals to the IP) in verilog, and a 'top' module that connects the two together. The design needs an external clock, which I will supply and I found which pin I need to use to get a universal clock.
I have two questions:
1) The IP as a asynchronous reset, and the documentation says 'Asynchronous reset of configurable polarity. Assert, if PixelClk and SerialClk are not within spec.'. The comment next to the source code itself says 'asynchronous reset; must be reset when RefClk is not within spec'. Can someone explain exactly what this means in simple English? I could not find any signal called 'RefClk' in the design. Practically, what should I do with the reset?
2) I attached a picture of the synthesis schematic from Vivado. Now, my video generator has a video data output of 24 bits (3 8 bit RGB values), and the IP has a video data input of 24 bits. So what are the D and Q signals coming out of the video generator, and why are they 2 bits each?
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