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Zybo Z7 LED5 turning ON when constraints of I2S clock are enabled

Question

I'm designing an application using the Audio CODEC of the Zybo Z7. I'm configuring the CODEC by I2C properly and could see data coming from the I2S.

Then  I realized that each time I programmed the FPGA, the Led 5 of the board was turning ON... even this LED is not at all part of my design!! Never mentioned in my constraints and never mentioned in the verilog wrapper.

Then proceeding by elimination when analyzing the constraints, I realized that this LED was turned ON as soon as the I2S clock went enabled...

with below constraints: NO LED TURNED ON

##I2S Audio Codec
##set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports BCLK_0]; #IO_L12N_T1_MRCC_35 Sch=AC_BCLK
##set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports FCLK_CLK1_0]; #IO_25_34 Sch=AC_MCLK
##set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports RECDAT_0]; #IO_L12P_T1_MRCC_35 Sch=AC_RECDAT
set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports RECLRCLK_0]; #IO_L8N_T1_AD10N_35 Sch=AC_RECLRC


##Audio Codec/external EEPROM IIC bus
set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports IIC_0_0_scl_io]; #IO_L13P_T2_MRCC_34 Sch=AC_SCL
set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports IIC_0_0_sda_io]; #IO_L23P_T3_34 Sch=AC_SDA
 

But with below constraints enabling the CLOCK... I get the LED turning on in Red, Green or Blue depending...

##I2S Audio Codec
set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports BCLK_0]; #IO_L12N_T1_MRCC_35 Sch=AC_BCLK
set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports FCLK_CLK1_0]; #IO_25_34 Sch=AC_MCLK
set_property -dict { PACKAGE_PIN R16   IOSTANDARD LVCMOS33 } [get_ports RECDAT_0]; #IO_L12P_T1_MRCC_35 Sch=AC_RECDAT
set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports RECLRCLK_0]; #IO_L8N_T1_AD10N_35 Sch=AC_RECLRC


##Audio Codec/external EEPROM IIC bus
set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports IIC_0_0_scl_io]; #IO_L13P_T2_MRCC_34 Sch=AC_SCL
set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports IIC_0_0_sda_io]; #IO_L23P_T3_34 Sch=AC_SDA

I'm respecting the pin allocation proposed in the Zybo Z7 manual... therefore I do not understand what is going on... Let me know if someone already faced this situation or have any idea of the phenomena.

I"m using Zybo_Audio_Ctrl IP for the I2S 

below a copy of my design...

image.thumb.png.6792407407b1d30716a108a520aabf5e.png

 

image.png

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