Does someone know how can I instantiate the STARTUPE2 primitive in a project that uses only TCL? I am working to port from Arty A7 to Arty S7 and notice the constraint file has missing qspi_sck signal, then the following appears at the Arty S7 .xdc file
## Note: the SCK clock signal can be driven using the STARTUPE2 primitive
But the project uses only tcl scripts. How can I workaround this?
I found HDLC and Verilog examples under UG953 but I have limited experience on how to use them using TCL.
Question
mhanuel
Hello all,
Does someone know how can I instantiate the STARTUPE2 primitive in a project that uses only TCL? I am working to port from Arty A7 to Arty S7 and notice the constraint file has missing qspi_sck signal, then the following appears at the Arty S7 .xdc file
## Note: the SCK clock signal can be driven using the STARTUPE2 primitive
But the project uses only tcl scripts. How can I workaround this?
I found HDLC and Verilog examples under UG953 but I have limited experience on how to use them using TCL.
Will appreciate any comments.
Best,
Link to comment
Share on other sites
4 answers to this question
Recommended Posts
Archived
This topic is now archived and is closed to further replies.