MIPI CSI-2 interface on Nexys-4 DDR board possible?

[koen.lostrie]

Hi all,

 

I'm trying to connect a MIPI camera (Rpi camera v2) to the Digilent Nexys-4 DDR board through the JXADC connector. Since these pins are routed for differential signaling, the JXADC connector seemed the best option for this, but I soon ran into a couple of problems though:

- the JXADC pins are not connected to any clock input pins on the Artix-7, so I get placement errors when trying to connect the MIPI clock lane to these pins. I found out there is only 1 P-version clock input pin available on all the PMODs, namely JB10 (which connects to H16 on the Artix-7), so I tried using JB10 & JB3 (N-version clock input) for the MIPI clock lane pair. I realize this pair will not be optimally routed for differential signaling, but it's the only option I can find.

- the JXADC pins all connect to bank 15 on the Artix-7, which is the same bank as the DIP switches and LEDs. This gives errors when trying to use LVDS_25 on the JXADC pins, while also using the DIPs and/or LEDs, since they are LVCMOS33 and you can't have 3.3V as well as 2.5V on the same bank.

Then I've seen a couple of posts on this forum from zygot, stating there are a lot of problems with this, which got me a little spooked. I didn't understand ALL of what is said on his posts, so the question I would like to ask here is:

Is it at all possible to connect a camera with MIPI CSI-2 interface (2 data lanes, 1 clock lane) to the Digilent Nexys-4 DDR board or shouldn't I bother trying to get it work?

I already constructed a small PCB following to the Xilinx XAPP 894 application note to make a D-PHY compatible connection to the Artix-7 pins, but now I'm afraid the board itself won't allow it. I've already spent some time on this, so I just want to make sure I'm not wasting any more time if it is not at all possible.

Thanks in advance for your expertise.

Koen

[BogdanVanca]

Hello @koen.lostrie,

From my experience I can tell you that this is not feasible at all. There are a lot of problems with this along with those that you are already facing. For example you need to add termination resistors for the D-PHY lanes. Also the XADC has input serial resistors that will negatively affect your signals, and you probably need to get rid of them. 

We have done some signal integrity tests, and I can tell you that for what are trying to do is impossible to have a working project for a clock frequency higher than 210 Mhz. I am not going to enter here into more details. I consider that, the best solution for you would be to buy a Zybo-Z7 and use the onboard mipi-connector. 

 

PS:  You can have  LVCMOS33 and LVDS_25 on the same bank if you are using LVDS as inputs with the DIFF term termination OFF.

[jpeyron]

Hi @koen.lostrie,

I have not used the RPI camera V2. Looking at the schematic i could not tell if the clk is an input or an output. I know that you can take lvds 2.5v input into the Artix 7 fpga even if the bank is set at 3.3v. You can not send LVDS 2.5V out to the camera when the Bank is set to 3.3v. 

thank you,

Jon  

[koen.lostrie]

Hi @jpeyron,

thanks for your quick response. I'm quite sure the clock is output from the camera board to the Digilent board, since the Xilinx MIPI CSI-2 Rx subsystem manual states on page 12 that the clk_lane_rxn and clk_lane_rxp are both input to the IP block. So the question remains how to connect these to the Digilent Nexys-4 DDR board.

The only data going TO the camera board goes through an I2C connection, which works fine by the way.

Thanks again,

Koen

[jpeyron]

Hi @koen.lostrie,

I reached out to more experience engineers to see if they have any input for you.

thank you,

Jon

[koen.lostrie]

52 minutes ago, BogdanVanca said:

Hello @koen.lostrie,

From my experience I can tell you that this is not feasible at all. There are a lot of problems with this along with those that you are already facing. For example you need to add termination resistors for the D-PHY lanes. Also the XADC has input serial resistors that will negatively affect your signals, and you probably need to get rid of them. 

We have done some signal integrity tests, and I can tell you that for what are trying to do is impossible to have a working project for a clock frequency higher than 210 Mhz. I am not going to enter here into more details. I consider that, the best solution for you would be to buy a Zybo-Z7 and use the onboard mipi-connector. 

 

PS:  You can have  LVCMOS33 and LVDS_25 on the same bank if you are using LVDS as inputs with the DIFF term termination OFF.

Thank you @BogdanVanca, for this definitive answer! That saves me a lot of time and effort.