Zybo Z7-10 HDMI Input/Output Demo for Vivado 2017.4

[dpaul]

Hello,

New to this forum and my first post.

I want to run the HDMI demo by following this: https://github.com/Digilent/Zybo-Z7-10-hdmi

However this is for Vivado 2016.4 .

Now I want to modify the TCL script so that I can run this DEMO using Viv2017.4. I have run into problems while trying to run it directly (if needed I post the error details).

1. Does a migrated project already exists?

2. If <1> is false, then how can I migrate the TCL script? Any guidelines, references?

Thanks.

 

 

[jpeyron]

Hi @dpaul,

Welcome to the forums. We do not have an upgraded project for the Zybo-Z7-10-HDMI. This is on the to-do list for our content team. In general, once you have loaded the project into Vivado 2017.4 you need to upgrade/generate the ips(tools->reports->report ip status), generate a wrapper. Then generate a bitstream. I am in the processes of doing this with the project in vivado 2017.4 for verification.

Thank you,

Jon

 

update: My project generated a bitstream but it took quite some time. 

[dpaul]

Hi @jpeyron,

That means for me, the easiest way out would be to install Viv2016.4 and generate the project using the TCL script.

Then upgrade to Vivado2017.4 and upgrade the project accordingly, right?

I would have loved to modify the TCL and start the project using Viv2017.4, but I am always working in Vivado project_mode and have no experience in working with TCL_mode.

 

 

[Andy7777]

I'm just in the process of trying this also - just don't forget to copy the Digilent vivado-library files into the /repo folder like I did . I have managed to upgrade the IP cores, but there do seem to be an awful lot of unconnected pins, which is presumably because some of the core pinouts have changed.

Unconnected pins seem to be OK, should be connected automatically. I had to change the dvi2rgb core to 720p and the clock constraint on the hdmi input clock of 13.468 ns.

Took 3 hours  to build though, and still have a load of timing violations.

 

 

 

[jpeyron]

Hi @dpaul,

The process described above was all done in Vivado 2017.4. As @Andy7777 described it took a lot of time to generate a bitstream. 

thank you,

Jon

 

 

[Andy7777]

Just as a follow-up to this question, the build time issue is due to a missing global clock buffer on the clock pout of the zynq core - see the design in the Zybo-z7-10-base-linux project for how to fix it by adding a ds_util clock buffer