• 0

nexys video olead problem


Question

hi everyone, 

        Here is a screenshot of a microblaze based system using nexys video, controlling the OLed, when I validate and generate output products, I get this message : 

 [IP_Flow 19-4965] IP PmodOLED_axi_gpio_0_0 was packaged with board value 'digilentinc.com:arty:part0:1.1'. Current project's board value is 'digilentinc.com:nexys_video:part0:1.1'. Please update the project settings to match the packaged IP

        If I ingnore this , the systhesis works well, but during the implementation a bunch of errors and warnings appear? could anyone help me?image.thumb.png.79794f9e99208dbeb6181c285a1f5f9d.png

Edited by sosso
Link to post
Share on other sites

21 answers to this question

Recommended Posts

  • 0

hi jpeyron,

     That's the problem, the synthesis works perfectly, but the implementation is full of errors and warnings, so I can't generate the bitstream without passing by the implementation

                 is this related to the warning of the arty board?

                                       

Edited by sosso
Link to post
Share on other sites
  • 0

hi jpeyron,

             --[Vivado_Tcl 4-16] Error(s) found during DRC. Router not run.

               --[DRC PDRC-43] PLL_adv_ClkFrequency_div_no_dclk: The computed value 400.000 MHz (CLKIN1_PERIOD, net clk_out1) for the VCO operating frequency of the PLLE2_ADV site PLLE2_ADV_X1Y3 (cell design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_ddr3_infrastructure/plle2_i) falls outside the operating range of the PLL VCO frequency for this device (800.000 - 1600.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please adjust either the input period CLKINx_PERIOD (10.000000), multiplication factor CLKFBOUT_MULT_F (4) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.

 

         ---[DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk: The computed value 400.000 MHz (CLKIN1_PERIOD, net pll_clk3) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X1Y3 (cell design_1_i/mig_7series_0/u_design_1_mig_7series_0_0_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i) falls outside the operating range of the MMCM VCO frequency for this device (600.000 - 1200.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please run update_timing to update the MMCM settings. If that does not work, adjust either the input period CLKINx_PERIOD (20.000000), multiplication factor CLKFBOUT_MULT_F (8.000000) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device.

Link to post
Share on other sites
  • 0

Hi @sosso,

It looks like your mig is connected wrong. For using the QSPI i usually follow this old tutorial with a few changes for the vivado portion. On step 3.3 i do not select the interrupt controller. On step 4.4 i also add a 3rd output clk at 50 MHz.which is connected to the ext_spi_clk on the qspi ip core. On step 5 i would also add the qspi ,oled and led's based on you block design. On step 9, make sure your mig is connected as it is shown in the image in regards to the reset and output clk 2 of the clocking wizard. Once you have generated a bitstream and exported the hardware/launched sdk then i follow this tutorial. Instead of using the hello world template you will select empty and add the main.c from the examples of the oled ip core to the scr folder of the application. If you are also wanting to use the uart and gpio-leds you will need to alter the main.c that you added to the scr folder for the gpio and uart to work.

thank you,

Jon

Link to post
Share on other sites
  • 0

hi jpeyron

thank you so much that helped   a lot, the implementation works , but now I get problems in the bitsream, i get errors while generating bitstream ?

here is one of the messages:

  [DRC NSTD-1] Unspecified I/O Standard: 1 out of 66 logical ports use I/O standard(IOSTANDARD) value "Default", instead cause I/O contentiojn or incompatibilty with the board power or connectivity affecting performance .....

Edited by sosso
Link to post
Share on other sites
  • 0

hi jpeyron, 

     here is the block design : image.thumb.png.f95b6c1e4c538addae628478200c6c09.png

 

image.png.da1c81aa721590be3025bd73acffc016.png

image.png.41a339c6e000d3ab03db75c62361f228.png

image.png.142108c541d71dc1e4fd369173a43120.png

I tried both, when implementation to parameter some feature concerning the bitsream, the frequency of 33 mhz .. , and I tried also not doing anything but it doesn't work?

 

                                                                                        thank you 

 

image.png

Link to post
Share on other sites
  • 0

Hi @sosso,

Looking at your block design you should remove the sys_rst  connected to the mig and run connection automation.  you should look at the block designs in the getting started tutorial i linked above as a reference. 

thank you,

Jon

 

 

 

Link to post
Share on other sites
  • 0

Hi @sosso,

Here is a project that matches the ips in your block design done in Vivado 2017.4 for the Nexys Video. I have gone as far a step 3.1 in the How To Store Your SDK Project in SPI Flash tutorial since i do not have a Nexys Video where i am at.

cheers,

Jon

Link to post
Share on other sites
  • 0

Hi @sosso,

You will need to change the ip repository to the path of vivado library on your PC if you are wanting to open the block design in vivado. I attached a block design below. Once in sdk start on 3.1 of the tutorial. 

cheers,

Jon

 

Sosso_nexysVideo.jpg

Link to post
Share on other sites
  • 0

hi jpeyron, 

        4 GB of ram, now i tried the small tuto you adviced me , without oled without qspi implemented, It's been an hour since I runned the synthesis, 

It didn't finish yet 

Edited by sosso
Link to post
Share on other sites
  • 0

hi jpeyron,  

       I removed vivado 2017.4 and replaced it with 2016.4, it works perfectly , no errors, no latency during synthesis nor in implementation, much faster than 2017.4, I think I dindn't install very well the 2017.4, and it was so slow,  so thank you so much for you precious help , do I have to put this subject as solved?

Link to post
Share on other sites
  • 0

Hi @sosso,

You can click the grayed out check mark box on the left hand side of the post that you feel was the "Best answer"; this will help show the thread has been answered. Otherwise, there isn't another formal way of showing this (aside from editing your original question title to include the word "solved").

Thanks,
JColvin

Link to post
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now