Zybo HDMI untouched design not meeting timing req.

[Casio342]

I tried to synthesise the Zybo HDMI In project https://github.com/Digilent/Zybo-hdmi-in for the latest Vivado 2017.4.1. Without changing anything from the Block design and just upgrading all IP Cores in order to start the synthesis, the timing will not be met:

hdmi_in_i/axi_vdma_0/U0/GEN_SPRT_FOR_MM2S.MM2S_LINEBUFFER_I/GEN_LINEBUF_NO_SOF.GEN_LINEBUFFER.GEN_ASYNC_FIFO.LB_BUILT_IN.I_LINEBUFFER_FIFO/fg_builtin_fifo_inst/inst_fifo_gen/gconvfifo.rf/gbi.bi/g7ser_birst.rstbt/rsync.ric.rd_rst_reg_reg/C

Slack: - 6.327 ns

The IP Cores are generated globally.

 

How I can fix this problem? 

 

[jpeyron]

Hi @Casio342,

I believe you can ignore these timing issues. Are you able to complete the HDMI demo?

thank you,

Jon

[Casio342]

If I ignore these paths and program my Zybo-Board with that bitstream, the screen stays black. However, If I write the default bitstream file from the proj, it works..

Could you try to Synthesise the Proj and look if you get the same timing errors? 

[jpeyron]

Hi @Casio342,

I had to change the constraint file a little to get the project working in Vivado 2017.4.1 after upgrading the ip cores and generating a wrapper. From  ddc_sda_io to DDC_sda_io, from ddc_scl_io to  DDC_scl_io , from  iic_0_scl_io  to IIC_0_scl_io and from  iic_0_sda_io to IIC_0_sda_io.  I then generated a bitstream exported hardware and launched sdk. Once sdk was open i imported the HDMIK_in and HDMI_IN_bsp from the sdk folder in the project. I then programmed the fpga and ran as->launch on hardware(system debugger) to load application. It worked at my work station. Did you update the xdc file?

thank you,

Jon

[Casio342]

Yes, I did that and followed all the Tutorial Steps on the SDK, Still..getting black screen very strange. 

I will retest it on a different PC and report later. Thank you very much for your help JPeyron

[jpeyron]

Hi @Casio342,

For confirmation of getting the project working, it may be good to test out the project in Vivado 2016.4 since that is what it was designed in.

thank you,

Jon