AXI Stream FIFO

[newkid_old]

I am trying to read data into a AXI streaming FIFO.  I've attached my design.  The data is presented on the axi_str_rxd_tdata.  My clock that frames the data is applied to the axi_str_rxd_tvalid input.  I have a counter that counts up to 128 and when the limit is reached it pulses the axi_str_rxd_tlast line.  I am trying to read this data in my MicroBlaze processor but the only seem to catch one point of data.  The first word is the data I'm feeding the FIFO but the next 127 words are zero.  I am using Xilinx SDK example code for the fifo interaction.  Any help is greatly appreciated.

 

Cheers

[jpeyron]

Hi @newkid_old,

I have not work with the axi-stream fifo. I would suggest to look at the  AXI4-Stream FIFO v4.1 LogiCORE IP Product Guide. Might need to put in a delay after writing to read data.

thank you,

Jon

[newkid_old]

I suppose I should have framed this as a question.  Whats the best method to clock data in to a storage device?  Xilinx has a few choices and I'm not sure which is the best.

[jpeyron]

Hi @newkid_old,

Could you clarify what you mean by storage device and what your project is?

thank you,

Jon

[newkid_old]

I have an ADC that outputs a new number on the rising edge of a clock.  I want to store x number of samples, for now say 128, then read them into my Microblaze and spit them out over UART.

[jpeyron]

Hi @newkid_old,

The AXI Stream FIFO looks to be the best Memory device for your situation. Also to clarify what frequency are you planning on moving data from the ADC?

thank you,

Jon

[newkid_old]

80Mhz is my target speed.

[jpeyron]

Hi @newkid_old,

What is the clock frequency you are giving the AXI Stream FIFO?

thank you,

Jon

[jpeyron]

Hi @newkid_old,

also how often you getting a full packet from the FIFO?

thank you,

Jon

[newkid_old]

The FIFO has a 100mhz clock on it.  The adc is generating a new word at 5mhz currently.  My counter is set to 512 which equates to a packet every 102uS.  This assumes I'm understanding that a packet is the number of words it stores before a packet flag is generated.

[jpeyron]

Hi @newkid_old,

I reached out to a more experience engineer with axi stream fifo. They looked through the tread. They were not sure why this issue is happening. They suggested that you reach out to xilinx support about this issue.

thank you,

Jon