Cmod A7-35T Quad SPI memory question and peripheral interfacing

[BYTEMAN]

Hi all,

I'm confused about storing bitstream into the SPI memory that is on board and how to use a SPI bus to interface external peripheral.

To be more specific if I need to use the on board SPI memory (IC3 on the schematic board) to store my bitstream I've to add the AXI Quad SPI attached to my Microblaze or this memory is adreessed automatically from the FPGA at startup?

If instead only use the on board SPI memory to store my bitstream and then autoconfig the FPGA on startup I need to drive external SPI peripheral (e.g. and DAC) I've to add the AXI Quad SPI and then drive it from Microblaxe through the AXI mapping?

I'm a little confused about this point...

[EDITED]

I'm reading again the Cmod A7 manual (MANUAL) and I've found some information into the paragraph 2.2 and Chapter 4.

if I've correctly understand I can use the SPI memory to store my FPGA program without need to instantiate the AXI Quad SPI bus because this task will be do automatically on the FPGA startup (this sound also logic if I've a design that not need of a microblaze core, lika a simple logic as the button example, provided from Digilent), but if I need to store some data into the SPI memory, e.g. configuration data for my application I can read the SPI through the Microblaze into the adreess not used for the bitstream, my think is correct?

Also if I need to use an external peripheral different than the on board memory (like a serial DAC) I'll use another AXI Quad SPI bus and then set the physical FPGA outputs for it through the XDC filles, e.g. using some pio pins. Is correct?

Make sense?

Thank!

[jpeyron]

Hi @BYTEMAN,

The Cmod A7 Programming Guide shows how to program the Cmod A7  flash with a project not using microblaze. The How To Store Your SDK Project in SPI Flash tutorial shows how to program the flash using microblaze and the quad spi flash(ext_spi_clk on the ip core needs a 50 MHz clock from the clocking wizard).  if you need to use an external peripheral different than the on board memory (like a serial DAC) you would use one of the axi ip cores depending on the type of communication the serial DAC is using i.e. spi, i2c, uart, gpio. You would set the physical FPGA outputs for it through the XDC filles, e.g. using some pio pins. We have many different examples in our vivado library of how we facilitated the different communication along with sdk code to use the different pmods. We abstract a lot of the communication complexity from the hardware side of the design using the pmod bridge and the board files. If you are trying to learn how to use the axi quad spi ip core I would first start by looking at the AXI Quad SPI v3.2 LogiCORE IP Product Guide.

thank you,

Jon