Cmod A7-35T Microblaze design and output pins

[BYTEMAN]

Dear all,

I'm still working on a example design where I've a microblaze, one UART, some RTL logic defined by VHDL files and connected to the Microblaze.

Now I'm try to connect some signal to some output of the Cmod A7-35T board.

Here the schematic:

Concerning the sys_clock I can see the constraints into the board file for the Cmod A7-35T board hence I think this is ok and no need to specify it directly.

About the others pin, in order to connect it to a FPGA pin I've used this procedure:

- select a pin and then make a right-click

- from the menu select the Make External menu entry

this make a port with a default name liek the one used into the output pin of the logic block where the pin came from.

Now I've to associate a logical pin with a hardware pin of the FPGA.

to do that I've loaded as new contraints file the xdc board files provided by Digilent and then I've unmarked the following lines:

then I've changed accordling these names the one on the graphicl view in order to match the one into the XDC file.

To change the name assigned as default to a pin into the graphical view of the system I've do right click on the port and then I've selected the External Port Properties menu entry.

On the left side of the design view I've changed the default pin name with the name that I can found into the XDC file for the pin that I've choose to use, in this example the pio4 pin.

QUESTION #1

Now I'm asking to expertes if my steps are correct in order to setup all the input/output physical pins used into a design.

QUESTION #2

About the reset pin that is used for the MMCM generated by the Block Design when I've configured the microblaze for the first time I've a doubt, this pin is not listed into the XDC file board provided by digilent then I've to assign it to an external pin, like a pushbutton or this special signal is assigned internally to the reset circuitry of the FPGA? Where I can found more info on the subject?

QUESTION #3

There is a way to see the options used for the Microblaze soft core on the first wizard definition and then change it after the first definition?

Thank for your time and help.

Best regards

[BYTEMAN]

After the bitstream implementation we can chek about the constraints from Implementation->Implemented Design->Edit Timing Contraints:

then the constraints for the clock was added automatically from the clocking wizard hence no need to add it manually into the XDC files (this will arise in a error).

 

[jpeyron]

Hi @BYTEMAN,

Reading through your post i do not see an issue with your process for making external pins and constraining them with the xdc. In regards to the reset pin I reached out to one of our design engineers about this and they responded that the oscillator on the CmodA7 always runs so there is no way to stop or reset the input clock. If you want to reset the clock in a MicroBlaze design then you need to connect the reset pin of the MMCM block to an external pin, such as BTN0 or BTN1.

They typically tie the clock reset pin of the MMCM block to a constant in my MicroBlaze block designs. It’s either a constant ‘1’ or a constant ‘0’, depending on what the active state of the Reset is configured for.

You can see how we configured the microblaze for the cmod a7 35t by looking through the board files here. After you do block automation you can customize microblaze to your needs. The preset for microblaze that the board files facilitates configures microblaze for the cmod a7 so altering the setting can make issues with your design.

thank you,

Jon

 

[BYTEMAN]

8 hours ago, jpeyron said:

Hi @BYTEMAN,

Reading through your post i do not see an issue with your process for making external pins and constraining them with the xdc. In regards to the reset pin I reached out to one of our design engineers about this and they responded that the oscillator on the CmodA7 always runs so there is no way to stop or reset the input clock. If you want to reset the clock in a MicroBlaze design then you need to connect the reset pin of the MMCM block to an external pin, such as BTN0 or BTN1.

They typically tie the clock reset pin of the MMCM block to a constant in my MicroBlaze block designs. It’s either a constant ‘1’ or a constant ‘0’, depending on what the active state of the Reset is configured for.

You can see how we configured the microblaze for the cmod a7 35t by looking through the board files here. After you do block automation you can customize microblaze to your needs. The preset for microblaze that the board files facilitates configures microblaze for the cmod a7 so altering the setting can make issues with your design.

thank you,

Jon

 

Hi @jpeyron,

first of all thank for your answer now I can go straight with other step in my design.

I've also an important question about configuring the Microblaze after the very first instantiation by means of the block automation.

Now I need to review the settings of the Microblaze to be sure about memory settings, the options that I need to show and eventually change is the ones that is possible to set directly through the Run Block Automation as shown below.

But I can't fround a way to recall this wizard after the Microblaze was defined.

The only way that I have found to show the Microblaze properties was through the Customize Block from the contestual menu:

But in this wasy I have plenty of options and I've some difficult to get the right ones as shown into the Run Block Automation.

There is a easy way to match the settings that came with the Run Block Automation?

Could you give me some help also in this subject?

Thank for your time!

Best regards

 

[BYTEMAN]

I've another question about constraints concerning the physical pins of the peripherals that are listed with the board files.

For example, take the AXI quad SPI, I can insert it into the block builder and run the connection automation, about the physical pins allocation, I've to uncomment all the following rows into the XDC file or this is not needed because the board file is knowed from the VIVADO or I can uncomment and simply this overrides the default settings used from the board but due to these should be equals no drawback occour?

Same things about the cellular ram block.

Thanks for your help in better understanding.

Best regards

[jpeyron]

Hi @BYTEMAN,

I am not aware of a way to have those specific microblaze configuration pages to be used after the initial block automation. I would suggest to reach out to xilinx about this question. I believe you are correct about the xdc overriding the board file defaults.

thank you,

Jon

[BYTEMAN]

2 hours ago, jpeyron said:

Hi @BYTEMAN,

I am not aware of a way to have those specific microblaze configuration pages to be used after the initial block automation. I would suggest to reach out to xilinx about this question. I believe you are correct about the xdc overriding the board file defaults.

thank you,

Jon

Thank you @jpeyron for your help and time!

Best regards

 

[davidoff]

On 4/3/2018 at 10:16 PM, BYTEMAN said:

After the bitstream implementation we can chek about the constraints from Implementation->Implemented Design->Edit Timing Contraints:

then the constraints for the clock was added automatically from the clocking wizard hence no need to add it manually into the XDC files (this will arise in a error).

 

 

Thanks ByteMan for informative feedback. It's clear and easy to follow..

[BYTEMAN]

On 2/5/2018 at 10:17 AM, davidoff said:

 

Thanks ByteMan for informative feedback. It's clear and easy to follow..

You're welcome!

Don't know but may be interesting reading also this thread:

How to store SDK project in SPI flash (bootloader with Microblaze)

I've spent some time to figure out how keep this working, would be nice know the experiences from others to see if the results are similar or there are others think fo take in consideration.

Bye