Zybo Z7 PMOD IO speed

[GN_ghost]

I have a question about how to connect zybo z7 to a ADC with LVDS input and output running at 200MHz. The zybo z7 need to provide clock to the ADC at 200 MHz and receive data at this speed. The ADC's interface is indeed LVDS yet this zybo z7 board's IO bank are all 3.3V powered, which means that it cannot use the internal termination. I think I have two way to make it work.

1. transmit data and clock in a single-ended way and do the single-ended to differential conversion on my ADC board.

2. transmit data in LVCMOS33 and do level conversion in ADC board.

The problems I have are that:

1. Is that ok to transmit a signal in single-ended way at 200MHz? I have no experience on doing that before.

2. If I use LVCMOS33, since I still cannot use the on chip termination, is that enough for me to just terminate transmission lines at the ADC's LVDS driver side?

3. What is the impedance on the FPGA IO pins when it is in LVCMOS mode? 

 

Thanks a lot!

[jpeyron]

Hi @GN_ghost,

On page 31 in the reference manual in section 16.4 High-Speed Pmod is shows the High speed pmod ports traces are routed 80 ohm (+/- 10%) differential. We do not have a maximum frequency for the High speed pmod ports so we can not guarantee the 200 MHz. I am not familiar with the termination protocols with LVDS here is a document that might be helpful.  Here and here are some forum threads that also deal with this issue and should be helpful.

thank you,

Jon

[GN_ghost]

3 hours ago, jpeyron said:

Hi @GN_ghost,

On page 31 in the reference manual in section 16.4 High-Speed Pmod is shows the High speed pmod ports traces are routed 80 ohm (+/- 10%) differential. We do not have a maximum frequency for the High speed pmod ports so we can not guarantee the 200 MHz. I am not familiar with the termination protocols with LVDS here is a document that might be helpful.  Here and here are some forum threads that also deal with this issue and should be helpful.

thank you,

Jon

 

Thank you very much for your reply!

 

Well, I understand how to terminate a LVDS pair generally, but it just couldn't be implemented in this board. (adding resistor near the SoC)

Beside using the PMOD connector, I found that our camera MIPI connector indeed has proper termination (R49 R50 R51). Since the reference manual mentioned that the routing of D-PHY signals follows xilinx's app note, can I assume that those lines are 50 Ohm lines?

Quote

Manual:

6

MIPI CSI-2 Lane 1 (+)

Terminated and connected to 2 FPGA pins as described in XAPP894

 

Quote

XAPP894:

Two wires as a differential pair per data lane or data link and two wires as a differential pair for the clock lane or clock link.

° Four wires comprise the minimum PHY configuration (one data lane and one clock link).

° The characteristic impedance is 100 differential, 50 single-ended per line.

 

If it is 50Ohm lines, do you think it is possible to just remove R46 R47 R48 R54 R55 R56, and change R49 R50 R51 to 100Ohm resistors to convert those lines into LVDS pairs?

 

Thanks again.

[JColvin]

Hi @GN_ghost,

I have reached out to one of our engineers who is much more familiar with the design about your inquiries. They are out of the office at the moment though, so it may be a few days before I hear back.

Thank you for your patience,
JColvin

[JColvin]

Hi @GN_ghost,

I was able to confirm that the traces for CSI-2 connector do follow XAPP894 so that they are 100-ohm differential characteristic impedance. They also let me know that changing the resistors out as you described is possible and they expect it to work even better for LVDS signals than for MIPI, so long as you are okay voiding the warranty by making these modifications to your board.

One caveat that they did have though is that on the Zybo Z7 FPGA (both of them) the LVDS_25 I/O standard only supports inputs to the FPGA, so no differential output would be available.

Thanks,
JColvin