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nattib

offset to use into blconfig

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Hi everyone..

I 'm trying to figure out how to make my nexys video boot from qspi flash. I tried several offsets I found around the net...the sdk project build successfully as well as the programming of FPGA and flash (following the steps in the digilent tutorial)  but...nothing happens after that. i tried the same simple project  (the gpio example) without qspi and it works when " run as configuration" mode. Now i  suspect the offset used for flash image to be guilty. (my block design is just microblaze with debug module, gpio leds, uart (which i dont use in software), and the qspi with 50khz clock).

I am still a novice at this stage so i don't know how to debug my project. My questions:

-how to estimate a good  FLASH_IMAGE_BASEADDR for my nexys video card? (in theory I can only imagine that the size of the programming files would give me a hint but even here, i don't know how to move on 

-Any simplified steps to debug the app on the board?

....Thank you guys in advance, you are doing a great job helping the rest of mortals down here....

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Hi @nattib,

I was able to confirm the offset of 0x00C00000 works. Here is a completed project that puts the hello world uart template on the nexys video flash in vivado 2017.4. I will update the tutorial to reflect this. I have attached a screen shot of the tera term as well as the projects block design.

thank you,

Jon

nexys_video_qspi.jpg

nexys_video_qspi_2.jpg

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Hi Jon,

thank you for answering. any idea of what might be the cause of my project not working in hardware then? the qspi itself is fine because I tried it with a vivado only project, but with sdk sometimes it even never reach the step of creating the bootloader (finish button disabled) or as with this simple project everything looks fine until it reachs the step of running in hardware where it stucks....I will have a look at your project and try to compare mine with it if I manage to find vivado 2017 (I use 2016.4)....thanks a lot again!

Edited by nattib

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Hi Jon,

Actually, sdk doesn't show any error, the programming of the fpga and the qspi as well. I use the 50 MHz clock for ext_spi_clk.  the example is just blinking led 0 (on and off for a certain time). in debug mode it works and the change in blinking is relatively long but visible. I tried other simple examples where it never reaches the bootloader as if there was no qspi in the design although it is listed with the ips imported from vivado. 

 

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