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Tim S.

Zybo Z7-20 PCam-5C Demo timing closure

Question

The current ZIP-file release of the Zybo Z7-20 pcam-5c demo does not achieve timing closure with Xilinx Vivado 2016.4 .

The constraint from ZyboZ7_A.xdc:

create_clock -period 2.976 -name dphy_hs_clock_p -waveform {0.000 1.488} [get_ports dphy_hs_clock_clk_p]

does not achieve timing closure for two signal paths in system_i/MIPI_D_PHY_RX_0, both related to DDLY

A    B
Name    Path 62
Slack    -3.303ns
Source    dphy_data_hs_n[0]   (input port clocked by dphy_hs_clock_p  {rise@0.000ns fall@1.488ns period=2.976ns})
Destination    system_i/MIPI_D_PHY_RX_0/U0/DataLaneGen[0].DPHY_LaneSFEN_X/HSDeserializerX/Deserializer/DDLY   (falling edge-triggered cell ISERDESE2 clocked by dphy_hs_clock_p  {rise@0.000ns fall@1.488ns period=2.976ns})
Path Group    dphy_hs_clock_p
Path Type    Setup (Max at Fast Process Corner)
Requirement    1.488ns (dphy_hs_clock_p fall@1.488ns - dphy_hs_clock_p rise@0.000ns)
Data Path Delay    1.822ns (logic 1.822ns (100.000%)  route 0.000ns (0.000%))
Logic Levels    2  (IBUFDS=1 IDELAYE2=1)
Input Delay    4.250ns
Clock Path Skew    1.372ns
Clock Uncertainty    0.035ns

 

I would like to request information as to how I may solve timing closure for the MIPI_D_PHY_RX. This is an unmodified project.

 

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Hi @Tim S.,

I verified that you can ignore these timing issue with another co-worker. We just went through the project to confirm the project works which it does. 

thank you,

Jon

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Hi @jpeyron,

I followed the Digilent on-line documentation for the project and the demo is working on my board. Thank you for confirming in advance that the timing issue on the "special" IO Delay Buffer instances can be ignored. I will go ahead and read the relevant Xilinx App Note on the special IO Delay Buffer configuration for my own edification.

Best,

Tim

 

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A new user too -- trying to get familair with the docs and files.

I got similar timing closure problem as Tim did.

After following the instructions to download the demo project,

https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-z7-pcam-5c-demo/start

and following instructions below (used 'Vivado' option) to build w/o changing anything:

https://reference.digilentinc.com/learn/programmable-logic/tutorials/github-demos/start

After build/generate-bitstream, got total negative slack as -6.646ns and hold slack -2.03ns

@jpeyron:

 -- are you still suggesting to just ignore it?

 

 

 

 

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@jge64:

 

I have built the pcam example with Vivado 2016.4 and Vivado 2018.2 . With 2016.4 I observed an error with processing with RGB color space turned on. With 2018.2 I observed a refresh rate error at 15 fps.

I do not know if @jpeyron is accurate that the timing closure error is benign.

 

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Hi @jge64 and @Tim S.,

I ran the Zybo Z7-20 Pcam 5c demo without issues in both Vivado 2016.4 and 2017.4. I had negative slack in both Vivado versions. I have attached a screen shot to show this. In the section Pcam 5C Image Sensor and Post Processing Options  of the demo material for this project here discuss in option a  that 1080p@15Hz is not supported and in option d was included for debugging purposes and should always be set to RAW mode (option 2).  There currently is not a release or plans to release a Vivado/SDK 2018.2 version for the Zybo-Z7-20 Pcam 5C demo. Issues with upgrading projects to non-released versions of vivado are sometimes very hard to pin point where the problem is. 

thank you,

Jon

zybo-Z7-20-Pcam-5c_2.jpg

zybo-Z7-20-Pcam-5c_3.jpg

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