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Problems with MIG_7


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Has anyone had problems trying to use MIG_7 in their block diagrams in Vivado?  I had a design that was working under version 2015.3, then something went wrong.  Whenever I try to select that IP block in my diagram, vivado hangs trying to open it.  I tried deleting it from my design and bring in a new mig_7series block from my list of board components and it hangs as well.  I brought my design over onto a different Win7 computer and did a fresh install of a newer vivado 2017.3 with the latest board files with the exact same result- when I try to bring in the mig block, vivado hangs forever.

Anyone know which files in my design I can remove to eliminate the bad references to the mig_7?

tnx

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Sorry for such a vague question.  I am using the Arty board.  It's probably a file corruption problem and more related to Vivado, but for some reason all of a sudden (it used to work fine) when I bring up my block diagram and click on the mig_7series block it hangs forever while trying to open the block to re-customize.  I have even deleted the block, and when I try to bring it back in from the list of IP, the same thing happens- it hangs trying to load the block onto the diagram.  i have even brought my design into 2017.4 and same problem- it hangs trying to load that one module.  I can re-customize any other block in my design with no problems.  I think if I can just find where all the files for that IP are located I can replace them without having to re-install all of vivado.  Another hint is that I can't bring that mig_7series block into other designs either, without vivado hanging.  I can't seem to find any log file with a related error either.

thanks,

  dave

 

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My Arty board has the XC7A35T, running Vivado 15.3

This may be part of my problem.  I figured the mig file was corrupted so I re-copied the board files into the Vivado board files directory, and I used the ARTY folder from the vivado-boards-master.zip file called "New\Arty\C.0".  This got me out of that vivado hang (but only when I manually go through each step of implementation).

I think I should have used the ones from the arty-a7-35 folder, because now my gpio signal for shield_dp0_dp19_tri_io[10} disappeared from pin V17 (as the arty schematic shows also) and is now on pin C1 of the FPGA.  Should I be using "New\arty-a7-35\E.0" ?

thanks

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Actually, New\arty-a7-35\E.0\part0_pins.xml has the wrong io location for my board also:

  <pin index="64" name ="shield_dp0_dp19_tri_i_10" iostandard="LVCMOS33" loc="C1"/>

The file "old\board_parts\artix7\arty\C.0\board_part.xml" has the correct pin:

   <pin index="10" iostandard="LVCMOS33" loc="V17"/>

Perhaps I originally compiled with Vivado 2014.4, and now I have been using 2015.3?  Is this why the format of the board files are different?

I don't understand the V17 <-> C1 pin swap though.

 

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Hi @davec,

I know that board files we made differently for vivado 2014 than they are now. This could be the issue you are seeing. I am not sure about the pins swap but i do know that there was some timing issues with the mig 7 on the arty and to fix it we give the sys_clk_i a 166.667 mhz clock as shown in this older tutorial here.

thank you,

Jon

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Two years later, I want to use one of my ARTY boards for a new design.  After loading 15.3 on a new (win10) computer I have this old problem again where I can not bring in the mig_7series memory controller.  Also tried vivado 2017.4- same problem.  It hangs while trying to add mig to my design or re-customize it. I'm thinking it's a problem with mig.exe or related files in webpack.  Will try design edition since it looks like a problem similar to this post (although I am using Artix, not Spartan):.

 

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