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rgb2dvi IP customization Part 2


I have two questions

1) According to Digilent documentation, the rgb2dvi IP is designed to take a minimum pixel clock of 40 MHz. 

My video data is at 27 MHz, so it seems to me that I will have to go into the original source code and try to make it work for a lower pixel clock

When I open the src folder of the IP, I open the rgb2dvi.vhd, which is the 'top module'. From there, all the parameters are taken.

See line 66- There are  3 options given

kClkRange : natural := 1;  -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3)

This parameter is taken to line 118, where it is fed into the ClockGen. It is interesting that the comment there says that the ClockGen can actually take 5 options

kClkRange => kClkRange,  -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5

And finally, inside the ClockGen.vhd file line 36 declares the parameter kClkRange, and confirms that it can take 5 options. But whatever is declared here is superceded by what is declared in the top module

      kClkRange : natural := 1;  -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3, >=30MHz=4, >=25MHz=5


So although the ClockGen clearly has five options,it seems that the IP itself is limited to three. Can someone please explain why and what will happen if I write '5' for kClkRange?

2) I now have to take these design files and add them to a new project in Vivado. 

I see that in the src folder of the IP, there are also three xdc files, and two of them actually have real code in them. What should I do with them? I plan on using a different xdc file to assign the pins on my board.

Edited by dgottesm
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Hello @dgottesm,

 If you look into rgb2dvi module you will found out, on line 36 this sintax:  "kClkPrimitive : string := "PLL"; -- "MMCM" or "PLL" to instantiate, if kGenerateSerialClk true". So, by default the clock primitive is instantieted as an PLL. For an 27 Mhz it is impossible to respect the minimum value for the PLL VCO frequency. Please check table 38 from the  attached document. But, it is possible to do it if you instantiante the clk primitive as an MMCM. In this case the low boundery for the  MMCM VCO frequency is 600.00 Mhz. For more details you can check the Table 37 from the same document. So, you need to chose  the value "5" for the "kClkRange", because that will outputs you an 675 Mhz frequency for the VCO (20 x 25). And that value  respects the MMCM constraints and also the project constraints.  Also, don't forget to set the 27 Mhz into the xdc file. A strong recommendation for you is to do all the modification manually into the vhdl's modules. And after that, if  everything looks ok and you want go further into the block-design, you can do the same stuff there with the help of the "edit in ip packager" option.

Answers for your questions:

1) Thats the minimum value if you instantiate the kClkPrimitive as an PLL.

2) For this question, you can take as an answer the above text. I hope I was clearly enough. 


I look forward to hearing from you.

Best Regards,

Bogdan Vanca 




Edited by BogdanVanca
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Hi @BogdanVanca

Thanks very much for your answer. 

For my first question, I understand that all I need to do is

1) set kClkPrimitive : string :="MMCM" and

2) set kClkRange: natural:=5;. Is that true?

For my second question, I did not understand your answer: What do I do with the 2 xdc files from the IP? Do I add them to my board xdc file? Where do set the clk to 27 MHz? (I am taking the clock from an external source)

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Hello @dgottesm,

On a first look, that's all that you have to do. Regarding to your second question, those  xdc-files sticks to your ip-core. There are locally with your ip and, if you want, you can modify them with the help of "edit ip packager" option. But that is not necessary, and in most cases it is not even recommended. You need to add your own xdc-file which will basically overwrite those, and will make, as you said all the pins assignments. To see the exact order in which your files are compiling please check the "compile order" tab, from the vivado menu. So, your 27 MHz clock needs to be set in your own xdc or, you can try to dynamically generate it with "axi_dynclk" module. I think that, the second option would be a better idea. There is another option in which you can use MIG 7 series (Memory Interface Generator). This core can generate up to 5 additional different clocks. But, you can consider this as an option only if you already/use or you are willing to use the memory generator in your block design.


Best Regards,

Bogdan Vanca

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