actual i try to transfer a data stream from the DMA via uart to my PC.
In my design an DDS-compiler generates a 32bit sine wave, which should be transfered via uart and read by a python script. The general data transfer works, but sometimes i get some noisy signal. This signal happens also when using a lower sample rate.
For the uart data transfer actual i did not add any marker where the 32 bit value begins or ends. So i expect this is the problem, but i don't know how to include this in my SDK and python code.
intXAxiDma_Poll_Uart(u16 DeviceId){intStatus,Index;intTries= NUMBER_OF_TRANSFERS;
u32 *RxBufferPtr;
u32 *RxPacket;
u8 BytesSent;RxBufferPtr=(u32 *) RX_BUFFER_BASE;RxPacket=(u32 *) RX_BUFFER_BASE;for(Index=0;Index< MAX_PKT_LEN_WORDS;Index++){RxBufferPtr[Index]=0xCC;}/* Flush the SrcBuffer before the DMA transfer, in case the Data Cache is enabled*/Xil_DCacheFlushRange((u32)RxBufferPtr, MAX_PKT_LEN);Status=XAxiDma_SimpleTransfer(&AxiDma,(u32)RxBufferPtr, MAX_PKT_LEN, XAXIDMA_DEVICE_TO_DMA);if(Status!= XST_SUCCESS){return XST_FAILURE;}while(XAxiDma_Busy(&AxiDma, XAXIDMA_DEVICE_TO_DMA)){/* Wait*/}/* Invalidate the TestBuffer before receiving the data, in case the Data Cache is enabled*/Xil_DCacheInvalidateRange((u32)RxPacket, MAX_PKT_LEN);//send data to uartBytesSent=XUartLite_Send(&UartLite, RX_BUFFER_BASE,sizeof(RxPacket));while(XUartLite_IsSending(&UartLite)){/*Wait*/}return XST_SUCCESS;}
Python code:
import numpy as np
import sys
import serial
buffersize =512
byte_number =4
ser = serial.Serial(
port='COM6',\
baudrate=921600,\
parity=serial.PARITY_NONE,\
stopbits=serial.STOPBITS_ONE,\
bytesize=serial.EIGHTBITS,\
timeout=0)for u in range(20):#read serial buffer
s = ser.read(buffersize)#convert to integerfor i in range (int(len(s)/byte_number)):
res_value = dataSerial[(i*byte_number):((i+1)*byte_number)]
value = int.from_bytes(res_value, byteorder='little', signed =True)
dataSerialFormated = np.append(dataSerialFormated, value)
Question
Weevil
Hi all,
actual i try to transfer a data stream from the DMA via uart to my PC.
In my design an DDS-compiler generates a 32bit sine wave, which should be transfered via uart and read by a python script. The general data transfer works, but sometimes i get some noisy signal. This signal happens also when using a lower sample rate.
For the uart data transfer actual i did not add any marker where the 32 bit value begins or ends. So i expect this is the problem, but i don't know how to include this in my SDK and python code.
Maybe any suggestion?
(The FPGA design is similar to my previous post https://forum.digilentinc.com/topic/8966-axi-dma-timing/?page=0#comment-26920 using the Cmod A7)
Plot of the result with pyqtgraph:
SDK code:
Python code:
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