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Adding Pmod NIC100 into Zybo device tree


gautam

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Hi Guys,

My application on linux requires two ethernet ports on the Zybo Z7 board. So I have recently bought a Pmod NIC100 card. I read the references and I have enabled the encx24j600 driver in the xilinx linux kernel. I have enabled SPI0 controller in vivado for the Z7 board.

Correct me if I am wrong, but I reckon to use the enabled encx24j600 driver, I have to add the interrupts and registers under spi parent in the device tree but I don't know the specifics of what I have to add.

Can someone please help me out? My intention is to get this board to appear as eth1 in xilinx linux. I would appreciate any other way than device tree method to do this as well. Let me know if you need any other information.

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Hi @jpeyron,

I don't mind accessing the Pmod NIC100 directly through the SPI interfaces available for the ARM processors on the Zynq chip rather than going through the FPGA. So I assume that I would not need an IP core for SPI and enc424j600.

I have enabled (as lkm) the encx24j600 driver available in the zynq linux kernel. Now that I have the following device tree for SPI1, I need to know what to add inside this tree to bind the encx24j600 driver to the enc424j600 chip on the Pmod NIC100:

spi1: spi@e0007000 {
            compatible = "xlnx,zynq-spi-r1p6";
            reg = <0xe0007000 0x1000>;
            status = "disabled";
            interrupt-parent = <&intc>;
            interrupts = <0 49 4>;
            clocks = <&clkc 26>, <&clkc 35>;
            clock-names = "ref_clk", "pclk";
            #address-cells = <1>;
            #size-cells = <0>;
        };

Let me also know if there is a different way to bind the encx24j600 driver to the Pmod NIC100 chip over SPI1 interface.

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@gautam

you'll need to add some spi slave node inside of the Zynq Spi controller.

Microchip sells another similar adapter and the documentation for it shows a slave node like this:

enc28j60: ethernet@0 {
  compatible = "microchip,enc28j60";
  pinctrl-names = "default";
  pinctrl-0 = <&enc28j60_pins>;
  reg = <0>;
  interrupt-parent = <&gpio3>;
  interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
  spi-max-frequency = <12000000>;
 

};

 

 

I've looked at the driver for the encx24j600 and it does not look like the driver responds to anything in the compatible string of the spi slave node.

 

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@gautam

 

I did find a device-tree fragment that someone else wrote for it this chip on BeagleBone Black.. There will obviously be some differences between that and Zynq, but it should be close enough to follow.

The project im referencing can be found here https://github.com/bwilcutt/encx24j600

spi1: spi@481a0000 {
  compatible = "ti,omap4-mcspi";
  #address-cells = <1>;
  #size-cells = <0>;
  reg = <0x481a0000 0x400>;
  ti,spi-num-cs = <2>;
  ti,hwmods = "spi1";
  dmas = <&edma 42
  &edma 43
  &edma 44
  &edma 45>;
  dma-names = "tx0", "rx0", "tx1", "rx1";
  status = "okay";
  interrupts = <125>;
   
  spi@1 {
  compatible = "microchip,encx24j600";
  status = "okay";
  spi-max-frequency = <1000000>; /* 1MHz */
  reg = <0x0>;
   
  /* Mapping encx24j600 to IRQ is done in-code. */
  };
 

};

 

Additionally, there is another overlay on that repo that handles the pin-control

 

encx24j600_pins: encx24j600_pins {
  pinctrl-single,pins = <
  0x190 0x33 /* spi.clk output */
  0x194 0x33 /* spi.d0 input */
  0x198 0x33 /* spi.d1 output */
  0x19c 0x33 /* spi.cs */
  /* Pin must be in GPIO mux_mode7 to be an interrupt */
  0x07c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* Interrupt from ENC chip, gpio1[29], P8_26 */
  >;
 

};

 

 

Unfortunately, this will be all that I will be able to help you with, but definitely look at that project as it should be a good starting point

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Just in case anyone else is looking for an answer to this question, I managed to get the Pmod NIC100 working with the following system-user .dtsi  file

I added encx24j600.debug=16 to the boot arguments to enable the maximum debug level in the ENCX24J600 driver (which needs to be added in kernel configuration)

 

ZYNQ PS SPI0 and GPIO0 (bit 0)  are used for the SPI and interrupt respectively

In the line

interrupts = <54 8>;

54 corresponds to GPIO0 bit 0 and 8 means active low level interrupt

 

/include/ "system-conf.dtsi"
/ {
chosen {
     bootargs = "console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait encx24j600.debug=16";
  };
};

&axi_uart16550_0 {
            clock-frequency = <100000000>;
            clock-names = "s_axi_aclk";
            clocks = <&clkc 15>;
            compatible = "xlnx,xps-uart16550-2.00.a", "ns16550a";
            current-speed = <9600>;
            device_type = "serial";
        };

&gpio0 {
    #interrupt-cells = <2>;
    interrupt-controller;
};

&spi0 {
  is-decoded-cs = <0>;
  num-cs = <1>;
  status = "okay";
   encx24j600: eth1@0 {
       compatible = "microchip,encx24j600";
       status = "okay";
       reg = <0>;
       spi-max-frequency = <10000000>;
       interrupt-parent = <&gpio0>;
       interrupts = <54 8>;
       };
 
};

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