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CKV

PMOD AD1 HDL codes

Question

Hello,

 

can I get the HDL files for the PMOD AD1? Exactly I need code which can take the AD1 outputs D0 or D1 to HDL module and gives me the output has 12bit number. so that I can process these 12bit numbers in subsequent modules.

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Hello,

 

The issue is I am trying use Pmod AD1 (ADC) for connecting to VCU118 pmod port, It is not giving an accurate conversion of analog input, the signal keeps changing (please see in the attached image) even when the analog input is constant?

What would be the exact reason for this? 

The same design I was implemented on the Nexys Spartan 6 board, it is working perfectly. Just I changed the XDC file for connecting to VCU118 (pins from AV16 to AT16)  

Many thanks.

adc.JPG

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Posted (edited)

Thank you, I have cross-checked the desigILA_AD1.thumb.JPG.c328e6984eb97e551e02f193a8fb636c.JPGn, I am attaching the image ILA_AD1.thumb.JPG.c328e6984eb97e551e02f193a8fb636c.JPGof observed signals on ILA, may help you identify the  probleILA_AD1.thumb.JPG.c328e6984eb97e551e02f193a8fb636c.JPGmILA_AD1.thumb.JPG.c328e6984eb97e551e02f193a8fb636c.JPGILA_AD1.thumb.JPG.c328e6984eb97e551e02f193a8fb636c.JPGILA_AD1.thumb.JPG.c328e6984eb97e551e02f193a8fb636c.JPGILA_AD1.thumb.JPG.c328e6984eb97e551e02f193a8fb636c.JPGILA_AD1.thumb.JPG.c328e6984eb97e551e02f193a8fb636c.JPG   

I have applied 1) 0V on D0 and 2) 3.3V on D1

image.png

Edited by CKV

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Hello Jpeyron,

I am using pmod in the default mode, I haven't done any level shifting, is that a problem? if so how to do the level shifting?pomd_pin.thumb.JPG.6315cdacbf9ca53a6f4d34965ba7a019.JPG e any level shifting, is

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Hi @CKV,

The PmodAD1 needs to be provided a clock between 10 Khz and 20 Mhz. The VHDL code we linked to above has the input clock as 100 Mhz. The system clock for the VCU118 is 300 Mhz so you need to make sure that you are only giving the AD1 module a 100 Mhz input clock. Also are you connecting the 0 and 3.3v to the J2 A0 and A1? If you are connecting the 0 and 3.3v to D0 and D1 on J1 this would be and issue as well.

thank you,

Jon

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Thank you for your reply.

I am providing 100MHz (10ns) clk to  VHDL module. when I am applying 3.3V between A1 and GND on spartan 6 it is showing FFFF and 0V between A0 and GND  it is showing 0000.

Similarly ( clock is 100MHz), I have done on VCU118 but the results are not correct.(shown in image )

Do you think is there any issue with the level shifter? I am using pmod in the default mode, I haven't done any level shifting.

   ILA_AD1.thumb.JPG.8fb29bde04723976db4c209c3b22ad1e.JPG

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Hi @CKV,

We do not have a VCU118 to verify what the default jumpers are set to. I would make sure that the jumpers are set so the Pmod port you are using is 3.3 v. Could you attach a screen shot of the block design, the wrapper and xdc in a text file as well as a picture of you set up?

thank you,

Jon 

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Hi @CKV,

I an not seeing an issue with your code. Are you using the same top_fpga_ad1 and pmodad1_test files with the spartan 6 board that is correctly working? Have you tried the using a zynq project and the add a module function. Here is a  forum thread that has a  project done by one of our community members attached called notarobot_ad1 done in vivado 2016.4 that uses an altered version of hamsters vhdl code and the add a module function to connect the hdl to the axi. I have also attached a screen shot of their block design.

thank you,

Jon

ADD_A_Module.jpg

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