Digilent Vivado Library is not supporting for VCU118

[CKV]

Hello, Digilent vivado library ( https://github.com/Digilent/vivado-library) is not supporting for Virtex ultra-scale + (VCU118), The board can support for the MicroBlaze and PMOD 

Can you please help me out?

[jpeyron]

Hi @CKV,

We do not officially support the ultra scale + with the vivado library. You should still still use the vivado library ip cores.You will need to open a project with a board selected from an already supported family (zynq, whatever), then add the IP to a BD, then edit in IP packager. Then go to the Compatibility Packaging step, "add family, check the "all families and parts" box and then to "review and package", repackage the IP.

You should then be able to change the target board and add the IPs you upgraded. Once you hae added the upgraded IP core to the block design you will right click on the pmod out of the ip core you are trying to use and select make external. Then after you have created a wrapper you will need to constrain the pmod out pin using the xdc for your board. 

thank you,

Jon

[CKV]

Thank you, I have proceeded according to your suggestions I am getting a follwing error?

Can you please help me out?

 

 

 

[jpeyron]

Hi @CKV,

You will also need to upgrade the pmod bridge as well. You will need to upgrade the pmod bridge first. You need to use vivado 2016.4 and have the licence for the ultra scale +.

thank you,

Jon 

[CKV]

Hello @jpeyron

I have upgraded the PMOD IP's for Virtex ultra scale+ (VCU118), How can I integrate this into my HDL design? (like for Xilinx IP's we have HDL stub, and I can instantiate stub in  my top HDL design ). 

It seems to me, I need to use an AXI protocol between my top design and PMOD IP. Do you have any examples design? (Like for SDK we have this https://reference.digilentinc.com/learn/programmable-logic/tutorials/pmod-ips/start) . 

 

Thanks in Advance

 

[jpeyron]

Hi @CKV,

We do not have and examples with the CVU118. Assuming you are using a microblaze design then it is relatively easy. If it is the Pmod Ad1 IP core then you just add the IP core  after you have added the microblaze IP. Typically I add the Pmod IP cores when I add the uartlite IP core to the block design. After you have added the IP core you right click on the pmod out and select make external and then run connection automation. Then finish your block design make a wrapper and then use and xdc to constrain the pins names that the wrapper assigns to the Pmod AD1 pins.

Then generate a bitstream and export the hardware including the bitstream. Then launch sdk. Once sdk is open make a new application with the empty template. Then move the main.c file from the examples folder of the Pmod AD1 drivers IP core( vivado-library/ip/Pmods/PmodAD1_v1_0/drivers/PmodAD1_v1_0/examples/) to the scr folder of the application. Then program the fpga and run the application.

thank you,

Jon