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pHSync, pVSync, and pVDE on rgb2dvi IP


Question

I am using the rgb2dvi IP of digilent, and I wanted to know exactly how to use the pHSync, pVSync, and pVDE signals that it requires as an input

I can understand that pVDE is high for the duration of active video, and low for the duration on non-active video

For pHSync, is it high for the duration of the horizontal sync?  Or does is it a single clock long? Does it go high on the same clock as pVDE goes low?

For pVsync, the same questions apply. Also, every end of a frame is also the end of a line, so do both pVSync and pHSync go high at the end of a frame?

Basically, my question is how these signals work together, and what they expect to be "fed"

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Hi @dgottesm,

As far as I know it is roughly a VGA stream, with an additional active_video flag. probably active high on the syncs and active_video (normal VGA has these active-low, I think)
the short version is that the IP is mostly intended to be used downstream from an AXI4-Stream to Video Out IP, and as such, we usually don't have to care about what those ports actually do. I have reached out to engineers  for familiar with the RGB2DVI IP to see if they have more input for you.

thank you,

Jon

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The length of the sync pulses is important, but if you know what they should be, and you have an "data enable" that is asserted during the active pixel session, then it is logically possible to regenerate the sync pulses, using the start of the active video periods and their length as a reference point.

You can count the pixels and lines, working out the format (e.g. 640x480, 800x600...) then use that to see when sync periods should start and end for standard video resolutions, and then use that to add your own sync signals.

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On how to use the IP, check the countless examples available on our Github page, even if not specifically made for your board: https://github.com/search?q=org%3ADigilent+rgb2dvi&type=Code

You can look at the block design and see where those signals are coming from. These are the synchronization signals adopted by DVI and HDMI from the analog world of television and VGA: http://www.cs.unc.edu/~stc/FAQs/Video/dvi_spec-V1_0.pdf

The sync signals can be generated by the Xilinx IP Video Timing Controller. The actual timing parameters are defined in VESA and CEA specs, which are not free, but a quick web search will turn up something for sure.

Also, here is a primer on VGA: https://learn.digilentinc.com/Documents/269

 

Edited by elodg
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@jpeyron @hamster

Do you mean to say that during the front porch, sync, and back porch, the video enable signal is zero, and only during the sync itself, are the sync signals equal to one?

Here is an interesting link to a VHDL code for a VGA generator. Is this the kind of thing I am going for?

http://lslwww.epfl.ch/pages/teaching/cours_lsl/ca_es/VGA.pdf

Thanks

 

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Hi @dgottesm,

Based on Elodg's response it appears that the pHSync, pVSync, and pVDE on rgb2dvi IP act just like the Horizontal sync, Vertical sync and data line in a traditional VGA project. Here is another web page that explains the vga process. I would suggest to look at the Github search Elodg links to for examples of how the rgb2dvi IP is used. Here is a more complex VHDL VGA project made for the Zybo that shows the different resolutions that might be helpful.

thank you,

Jon

 

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