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Using an external clock


dgottesm

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Hi

I am using a Zybo Z7-20 to collect video data which comes with its own clock. Meaning that it the video source has 8 parallel bits and a clock with which to sample them. My plan was to make the entire design synchronous to this external clock, but then someone told me that it can be problematic to use an external clock. Can anyone confirm this? I see that there are a lot of different kinds of clocks (bufg,bufio...) Can anyone give advice/tips/useful info on this?

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Hi,

I'd have to dig into the chip documentation myself but usually the first thing I'd check is that the intended clock pin is global clock capable. Clock signals have their own specialized "infrastructure" in the fabric, and most IOs do not provide a direct connection. Often it's visible from the FPGA pin name in the schematic (but as said, I haven't checked the specific documents for your board).

I can think of reasons why it wouldn't work in a more complex design (e.g. what deals with the error when the video source is faulty? How convenient is the frequency? What do I know about jitter, e.g. is it derived from a non-integer divider, possibly within a feedback loop to sync to some other clock).

That said, as long as I can avoid a clock domain crossing, I tend to avoid it...

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I'd start my research here (+schematic)

https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf

Actually I think this is independent of whether or not you use the clock for the logic - you need to get it into the circuit in any case (unless the external clock is so slow that I can oversample it with the internal clock. This works for SPI-ish signals, JTAG etc with near-unlimited timing margins but I wouldn't expect it for video).

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There's nothing problematic about using an external clock. If your video has a PCLK then you should use it. As @xc6lx45 pointed out your external clock should come into your FPGA on a pin that connects to the internal clock network. Xilinx has a naming convention to allow you to know which ones these are. I doubt that you really want to make your whole design one clock domain. The standard way to send data across a clock domain is to use dual-clock FIFOs. Figuring out how to do designs with multiple clock domains is a good skill to have, especially if you want to do video.

I suggest that you peruse the Xilinx literature and application notes to see how this is done.

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