Sampling with Pmod AD1

[luigee581]

Hello! I recently purchased the Pmod AD1 for the Zynq Z7-10 and I am trying to sample at 44.1 kHz. How can I set up a clock in the PL for this? Every time I set up a PL fabric clock to a multiple of 44.1 kHz, it is off by maybe ~500 Hz or more. Thank you in advance. 

[jpeyron]

Hi @luigee581,

Welcome to the forums. Which Zynq-Z7-10 board are you using? With the arty-z7-10 I was able to get an output clock from the zynq processor at .440917 using the io pll and 0441362 using the ddr pll.  There is another way to accomplish this. You do not need a clock at a multiple of 44.1KHz.  You need to initiate a SPI transaction approximately that often, and you need to make sure that your SPI clock is fast enough to complete a transaction/conversion cycle before you want to make another transaction
Instead of a clock, you could use an AXI timer to trigger an interrupt that initiates a SPI transaction and clears the timer at approximately the right rate.

thank you,

Jon