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Frequecny resolution of FFT is decided by FFT clock frequency ?

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Question

Hi,

I am am able to compute the FFT using IP core block available in Vivado 2017. However, whatever is the sample rate of input signal to FFT IPcore, the frequency resolution of the FFT is fixed by clock frequency of the FFT. Example

Frequency resolution  = sampling frequency/number of samples

DDS compiler generates sinusoidal frequency 976.56Hz at a clock freq of 1MHz,therefore the sample rate is 1Ms/s. this signal is given as input to the FFT IPcore 9.0 which is clocked at 5MHz with number of samples as 65536. therefore,

Expected frequency resolution = 1MHz/65536, however, measured frequency resolution  =5MHz/65536 in Behavioral simulation (Vivado 2017)

It does not matter what is the clock frequency of DDS compiler, the frequency resolution of the FFT remains at 5MHz/65536. But, in reality the frequency resolution is fixed by sample rate of input signals and the buffer size of FFT.

So, my question is, why in FPGA the frequency resolution is fixed by the clock frequency of FFT rather than sample rate of the input signal.

Help is much appreciated.

Regards,

Subash

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5 minutes ago, [email protected] said:

Wide FFTs?  If it requires tearing apart the Cooley-Tukey algorithm ...

Thanks sir for you help.  I dont undestand very well you question. For me I use IFFT of size 2048 cloked to 30.72 MHz, I choose a pipelined, streaming architecture, I use a scale factor to avoid ovrflow. The other IP is dds compiler cloked at 245.76 MHz generate a sin cos running at 30.72 MHz.  I am very grateful

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Your typical FFT accepts one sample at a time.  If you are operating at a 245 Msps rate, but then downclock that rate to something lower--say 50Msps, then each clock period will need to convey five samples.  You would then need to place five samples into the FFT per clock cycle.  Few FFTs can handle this.  Building an FFT that can handle five input samples at once is non trivial.  I've done it to build an FFT that can handle two incoming samples at once, so I know some of what is involved.  It's doable, but it will take some significant work.  If you go this road, you will either need to hire some (expensive) help, or dig into how the Cooley Tukey Fast Fourier Transform works in order to replace and re-implement pieces of it.

Your language above, however, is quite confusing.  You are generating a 30MHz signal at 245 Msps, but then want to process this signal at 30MHz?  Wouldn't that violate the Nyquist sampling theorem?

You may need to go back to the drawing board and rethink what it is you wish to do from the beginning.  What you are asking to do is not trivial.  It is doable if you know what you are doing, but judging by your questions I'm not sure you are ready to dive into a problem this complex.  My worry is that I will just spend hour after hour coaching you through the minute details of doing something like this and ... I have better (paid) uses for my time.

Dan

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22 minutes ago, [email protected] said:

Your typical FFT accepts one sample at a time.  If you are operating at a 245 Msps rate, but then downclock that rate to something lower--say 50Msps, then each clock period will need to convey five samples.  You would then need to place five samples into the FFT per clock cycle.  Few FFTs can handle this.  Building an FFT that can handle five input samples at once is non trivial.  I've done it to build an FFT that can handle two incoming samples at once, so I know some of what is involved.  It's doable, but it will take some significant work.  If you go this road, you will either need to hire some (expensive) help, or dig into how the Cooley Tukey Fast Fourier Transform works in order to replace and re-implement pieces of it.

Your language above, however, is quite confusing.  You are generating a 30MHz signal at 245 Msps, but then want to process this signal at 30MHz?  Wouldn't that violate the Nyquist sampling theorem?

You may need to go back to the drawing board and rethink what it is you wish to do from the beginning.  What you are asking to do is not trivial.  It is doable if you know what you are doing, but judging by your questions I'm not sure you are ready to dive into a problem this complex.  My worry is that I will just spend hour after hour coaching you through the minute details of doing something like this and ... I have better (paid) uses for my time.

Dan

@[email protected]  sorry for all my questions but why you told me that I vialote the nyquist sampling theorem

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Do you know what the Nyquist sampling theorem is?

Dan

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2 hours ago, [email protected] said:

There are three general methods for crossing clock domains.  The first is a 2-flip-flop synchronizer.  The second is a word synchronizer, built using a 2FF synchronizer to handle the flags, and the third is an asynchronous FIFO (others in this forum would call it a multi-synchronous FIFO).

As a generalization I agree. The double clocked synchronizer is common practice but not necessarily robust enough for all applications. Really this topic can get quite complicated. As for dual clock FIFO flags there are known timing uncertainties and usually you can avoid them in a system approach.

I'm in total agreement with @[email protected]who, if I'm reading him correctly, is suggesting that adding complexity to a complicated design approach is asking for more issues ( more difficult issues as well ) to figure out and resolve than anyone really wants to face. Elegant alternatives to complicated solutions are generally better and where one ends up at the end. A lot of general concepts seem workable until you start using them in physical implementation.

My advice is to figure out a system level approach that has easier implementation requirements.

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2 hours ago, [email protected] said:

Do you know what the Nyquist sampling theorem is?

Dan

@[email protected] the sampling frequency should be grater than fmax*2. Or the sampling frequency of fft is 30.72 MHz and my input signal sin cos is 30.72 MHz.

I did not think about this criteria. If I want to resolve this problem, I should have a sine cos more the 2*30.72MHz

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On 10/9/2020 at 4:48 PM, [email protected] said:

You may need to go back to the drawing board and rethink what it is you wish to do from the beginning.

Dan

@[email protected]Hi Sir, apologize for my different questions. I started again from the beginning, I clocked my different IPs to the same clock (30 MHz).

Configuration of DDS compiler:

System clock frequency=30 MHz, phase width=12, phase data= 64.

Using this configuration, the dds generates a 0.4675 MHz sine cos

Configuration of IFFT target clock frequency=30 MHz, target data throughput=30 MSPS.

When I try to compute a small IFFT of (8,16,32) of the generated signal from the dds compiler, the result of computation is correct compared to Matlab.

The problem is when I increase the size of IFFT (64,128, 256,1024), I have incorrect results. I don’t know why? Or I respected the Nyquist theorem (0.4675 MHZ< sampling frequency of IFFT/2=30/2=15). I cannot properly configure my dds to compute an IFFT of size 2048 ? I noticied by increasing the size of the FFT, I should further decrease output signal from the dds which correspond to the input data of the IFFT. I dont know why? A priori there is something I cannot understand. I am very grateful if you can respond me. Please sir have any clarification. Thanks.

Edited by jean
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On 10/9/2020 at 5:13 PM, jean said:

Your typical FFT accepts one sample at a time.  If you are operating at a 245 Msps rate, but then downclock that rate to something lower--say 50Msps, then each clock period will need to convey five samples

@[email protected] Dear sirs,

I have a somewhat stipulated question but I cannot understand it. please any clarification in my this example or any example I don't know why the data rate of each IP depends on its clock, the sample rate also depends on the clock. If an IP is cloked at 30 MHz it buad rate is 30Mbit/s if it is cloked to 245MHz baud rate is clocked to 245 Mbit/s. the sampling frequency is dependent on clock

Edited by jean