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Dear experts,

I have been working with the zybo hdmi in vga out project. Normally, It takes 24 bit vga signal, but I want to feed 16 bit grayscale as input (YUV 4.2.2) through vid in to AXI-4 Stream and 16 bit grayscale as output. Is there any solution for this? 

thanks-

Shuvo

Edited by Shuvo Sarkar

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As a side note, the normal format for DVID is RGB 444 (24 bits per pixel). You get 8 bits of each component each pixel clock.

If the FPGA board advertises that it supports HDMI and that it supports YCC 422, you will get:

  • 12 bits of Y0, and 12 bits of Cb on the first pixel clock (channel 1 carries the lower four bits of Y0 and Cr)
  • 12 bits of Y1, and 12 bits of Cr on the second pixel clock (channel 1 carries the lower four bits of Y1 and Cr)

If you want to get higher greyscale depth than 12 bits you will need to use a deep color mode. In the display port 1.4 spec deep colour modes supported are 24-, 30-, 36- and 48-bits per pixel, and only RGB 444 and for YCbCr 444 are supported.

Out of all the options, only 48-bits per pixel YCbCr gives you a 16-bit Y value, but it also doubles your data rate, making it not really usable with most low end FPGA dev boards - with generic I/O SERDES rated to about 1.2Gb/s you only use up to a 60MHz pixel clocks at 48 bits per pixel - not even enough for 720p images.

So as an upshot, if the best bet might just be to stick with RGB 444 on the interface using the existing solutions, and then do the transform into YCC within the FPGA design...

 

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13 hours ago, hamster said:

As a side note, the normal format for DVID is RGB 444 (24 bits per pixel). You get 8 bits of each component each pixel clock.

If the FPGA board advertises that it supports HDMI and that it supports YCC 422, you will get:

  • 12 bits of Y0, and 12 bits of Cb on the first pixel clock (channel 1 carries the lower four bits of Y0 and Cr)
  • 12 bits of Y1, and 12 bits of Cr on the second pixel clock (channel 1 carries the lower four bits of Y1 and Cr)

If you want to get higher greyscale depth than 12 bits you will need to use a deep color mode. In the display port 1.4 spec deep colour modes supported are 24-, 30-, 36- and 48-bits per pixel, and only RGB 444 and for YCbCr 444 are supported.

Out of all the options, only 48-bits per pixel YCbCr gives you a 16-bit Y value, but it also doubles your data rate, making it not really usable with most low end FPGA dev boards - with generic I/O SERDES rated to about 1.2Gb/s you only use up to a 60MHz pixel clocks at 48 bits per pixel - not even enough for 720p images.

So as an upshot, if the best bet might just be to stick with RGB 444 on the interface using the existing solutions, and then do the transform into YCC within the FPGA design...

 

Hi @hamster,

I have seen in SDSoC-platforms example the grayscale is applied, which takes rgb and weighted with graysale values. The code I found is following. Will it work in the hdmi in and vga out project sdk?

void DemoGrayFrameSw(u16 *srcFrame, u16 *destFrame)
  {
  u32 xcoi, ycoi;
   
  for(ycoi = 0; ycoi < DEMO_HEIGHT; ycoi++)
  {
  for(xcoi = 0; xcoi < DEMO_WIDTH; xcoi++)
  {
  u16 r, g, b, gray;
  u16 pxlIn, pxlOut;
   
  pxlIn = srcFrame[xcoi + ycoi * DEMO_WIDTH];
  r = ((pxlIn & 0xF800) >> (11-3));
  b = ((pxlIn & 0x07C0) >> (6-3));
  g = ((pxlIn & 0x003F) << 2);
  gray = (r * 76 + g * 150 + b * 29 + 128) >> 8;
  pxlOut = (((gray + 4) & 0x00F8) << (11-3)) | (((gray + 4) & 0x00F8) << (6-3)) | (((gray + 4) & 0x00F8) >> 2);
  if (xcoi < (videoCapt.timing.HActiveVideo / 2))
  destFrame[xcoi + ycoi * DEMO_WIDTH] = pxlIn;
  else
  destFrame[xcoi + ycoi * DEMO_WIDTH] = pxlOut;
  }
  }
  /*
  * Flush the framebuffer memory range to ensure changes are written to the
  * actual memory, and therefore accessible by the VDMA.
  */
  Xil_DCacheFlushRange((unsigned int) destFrame, DEMO_MAX_FRAME);
 

}

 

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The math will work (as you can expect):

     gray = (r * 76 + g * 150 + b * 29 + 128) >> 8;

I can't see any reason that it couldn't be integrated in the HDMI-in to VGA out project,

I have never looked at that project, but I suspect it will need to be implemented in a way that will fit nicely (be that an IP block, a HLS module or a VHDL or Verilog module).

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