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How to connect an external ADC to AXI Quad SPI


Mahdi

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Hello guys,

I am fairly new to FPGAs, but I have managed to get my Arty board to work with a bunch of Pmods through Vivado software with MicroBlaze. At this point, I am trying to use AXI Quad SPI for collecting data from an external ADC. I have my own 16-bit ADC (connected to a detector) which has an event flag pin that goes high when an event is detected. The flag is supposed to be latched high until the CPU responds and shifts out the 16-bit value. I wonder how can I implement such design inside my block diagram? I tried adding a SPI connector to my diagram, but as far as I see there is no pin on SPI block that I can connect my event flag to. Any help is highly appreciated.

 

Mahdi

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@Mahdi

I'd recommend that you connect the flag pin to an AXI GPIO controller and the normal SPI signals to your AXI Quad SPI IP. If you want to get fancy, you can add an interrupt controller and configure the GPIO controller for interrupts so that when the flag pin goes high, the CPU can drop whatever else it's doing to respond.

A bit of a side note, but you might be able to use our Pmod Bridge IP core (configured for top-row SPI and bottom row GPIO) to connect both of the AXI controllers to a Pmod port. Most of the SPI Pmod IP cores are just wrappers for these three IP.

Thanks,

Arthur

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@Mahdi,

The QSPI flash will take 5ms to program 256 bytes.  This isn't the same as writing to a memory, since programming a flash device can only turn the one's to zero's.  If you want to set a value within a flash to an arbitrary value, you first need to erase a sector of the flash (3s erases 64kB) which will turn the bits to all one's, and then you can program the flash at 256 bytes at a time.  Further, 3s to set a bit to a one and 5ms to set it to a zero is a very long time within most designs--long enough that it usually renders the flash as unusable for anything but a ROM type of memory.  (You can erase a subsector at a time in 800ms, but that's never been any help for me.)

I think you'd find it easier to write to a location on the DDR3 SDRAM of the Arty,

Dan

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@[email protected] @artvvb  

Thanks Arthur and Dan for your replies. Let me explain a bit more of what I am doing. I have an external 16-bit ADC which needs to be flushed every 1 microsecond. Normally, we use a SPI to communicate with the ADC, but it seems to me the Quad SPI on Arty is not designed for such purposes. Would it make sense to hard-code this in Verilog, or is there another IP which is better for this application?

Alongside this, the CPU is supposed to collect data from other Pmods as well, so I prefer not to use interrupts for this project.

-Mahdi

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@Mahdi,

Ah, so the SPI is not the flash but rather an A/D?  I would personally hard code the interface in Verilog.  You can find an example where I do so in this project--both with and without FIFO support.  It uses a WB bus however, rather than an AXI--so while it would be simple to connect this design to a ZipCPU, connecting it to your MicroBlaze would take a bit more work

Dan

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