A7-35T LVDS pins

[chm]

Hello there,

we are trying to use the A7-35T in an LVDS application, but it seems that the pin assignment on the DIL is not optimized for that, the differential pairs are in general not located close to each other.

Does anyone have a PCB printout so that we could choose those LVDS pins (we need only two pairs) that are the least badly routed?

Any experiences perhaps?

thanks

christian.

[zygot]

It's not just the PCB trace configuration from the FPGA to the PCB pins that you needs to worry about.  There are termination, bank voltage, power supply, and other details to take into account, not to mention the IO pins. If you have to have an LVDS interface with this board I'd suggest looking into LVDS-CMOS driver and receiver ICs. This will make your overall project more complicated and expensive... but the CMOD-A7 is a cheap and limited starting platform. Be aware of thermal issues as there isn't a lot of mass on the CMOD PCB or options for heat sinks. Again, the CMOD is almost ideal for a limited class of projects but not so for any project.

[jpeyron]

Hi @chm,

The Gerber files are not available to the public. Here is a forum thread that has the trace lengths for the arty pmod ports and the header. All of the i/o pins accessible to the user are 3.3v and are not adjustable.  My understanding is that the artix-7 fpga can use lvds input even if the bank is at 3.3v.  It can not do lvds output in this situation. Here is a forum thread that might be helpful.

thank you,

Jon