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Z7 board upgrade PMU?


mojs

Question

Hi everyone. 

I am curios if there is a relatively simple modification I can do to increase available FPGA power, especially the 1V into the FPGA, on a Z7-20 board?  

 

Background, my problem is simple. I load a design into the Zynq that is expected to drain much more on the 1V supply then what the PMU inside the board can deliver, when loaded the LD13 led goes down almost instantly indicating that the supply rails can't keep up. This is easy to do, just try to use half of the Fabric at a decent frequency (200+MHz) and you will have run out of power. So I assume the PMU was dimensioned for the smaller FPGA on Z7-10 originally. 

 

Regards

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Just curious... have you run a power analysis?
Getting the power into the FPGA is the first problem, but the problem of getting it out comes immediately after...

It is easy to create a gate toggle benchmark far beyond "most" reasonable use cases (bitcoin mining may be one of the exceptions). Trying to recall my own power analyses, most of the toggle probabilities were in the sub-percent range, not 50 %. On CMOS, power consumption is largely switching activity.

Also, is 200 MHz realistic? If I'm not mistaken, the 7000 Zynq is 28 nm, like the Artixes where reaching 200 MHz with a real-world design requires a serious effort (for speedgrade 1, and again, a simple systolic datapath as sha256 for bitcoin mining would be a notable exception but why would I use a Zynq for that).

 

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Oh, and the signal statistics may be too pessimistic:

Assuming you use a 1-0-1-0-1-0 on all gates, I get

  • 50 % rising edge
  • 50 % falling edge

But a (typical?) random signal has only

  • 25 % rising edge
  • 25 % falling edge
  • 25 % 1-1
  • 25 % 0-0

And the latter two draw essentially no power.

 

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Hi everyone, 

 

I am running from external power supply. 

 

I have noticed that if Xilinx Vivado built in power report estimates 2.8A on the 1V supply line it will not work, while 2.7A and lower seems to work fine. 

 

I am running the FPGA fabric as accelerators for the code running on the ARM cores. I am not doing any IO from the FPGA fabric (besides the AXI bus to the ARM cores). Currently I am running the fast clock in the FPGA fabric at 220MHz , going over that and the PMU cuts off. But I am amble to meet timing at 350Mhz for the fast clock in the design (fabric related to AXI busses are at 25MHz to not interfeer with the layout of the fast timed areas). 

Just a heads up, I am a complete noob when it comes to designing/using/testing on FPGAs.  I do have have over a decade of ASIC experience, but this was a lot more different then I expected it to be. 

I have gone over the layout boards, my thinking was if there was an exposed 1V connector somewhere that could be abused. My thinking was that I'm probobly better of getting a ZedBoard Zynq-7000 for further testing, but it seems to have even worse power constraints on the 1V line (even tough it seems to have a heat-sink)?  Or am I'm missing something?

 

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I'd suggest that you carefully monitor the Zynq substrate temperature during operation using the internal XADC. Generally, it's better to design ( or choose ) a board for high performance applications than coax one designed for general purpose hobby/teaching use to perform above its design limits. Of course that comment was obvious... but in the context of this discussion seems appropriate.

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Check if there are any large capacitors on the 1 V rail. Usually it's easy to attach a wire to one end of the SMD capacitor.

I've done that (but not with the same board) to get power out. When feeding power in, the power-up sequence may need to be observed.

BTW, I'm no AXI guru but I remember the ARM document stating that you can insert any number of registers into any path (address, write data, read data) because of the two-way handshake, to clock it at higher rates.

If you need an industrial module, one possible supplier (and Digilent distributor) is https://www.trenz-electronic.de/.

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