BLOCK Design VIVADO UD CNTR Q[?:?] to Discrete logic [?:?]

[DigitalConfig]

Hello,

        I have written many VHDL configurations, however, I am now working with block designs on VIVADO and am having trouble figuring out how to interconnect a binary counter with outputs Q[8:0] to inputs discrete logic ANDs ORs NOTs of various [?:?].  I need to do this so that I can determine multiple output values of the 9bit count. I would also need to know how to do this for other discrete logic circuits.   Also any information about using wrappers to import the design into a VHDL usage would be helpful as that would be the next step.  The specific trouble seems to be that when I connect Q[8:0] to OP[3:0] it just draws a bus and doesn't specify which actual pin configuration is present nor how to select which it should be.  I have also gone thru several Xilinx reference materials on VIVADO and none of the techniques I have found demonstrate nor explain how to do this specific task.

Thank you in advance Sincerely

DC

PS. 2 more considerations after I created this post 1) placing this circuit into a stand alone block IP circuit 2) Interconnecting directly TO FPGA IOs

[artvvb]

@DigitalConfig

You can use the Slice IP to extract specific bits from a bus, multiple slices can use the same bus as input (screenshot below). You can use the Concat IP to merge multiple buses together. Designs using a bunch of these IPs can get messy. The other option for doing any of this is to use the "Add Module" option in the right click menu in IPI to add a custom HDL module you have written into the IPI design. There's a lot of little features relating to adding HDL modules, but without going too deep, standard_logic_vectors are interpreted as a bus of the specified width.

To connect a design to FPGA I/O, use the "Create Port" interface and constrain the ports with an xdc file.

Thanks,

Arthur

[jpeyron]

Hi @DigitalConfig

Based on your other threads are you using the Arty-S7-50? Here is the master xdc for the Arty-S7-50. On the blocks that you want the output to go to pins on the board you right click on the out bus and select make external. Once done with your design you select the source tab and right click on the design block and select create a wrapper and click ok. Then you use the xdc to constrain the pins names generated in the wrapper with the xdc.

thank you,

Jon

[DigitalConfig]

thanks guys I think that helps till my next hang up which I hope I don't have.

btw I have a arty a7-35 Jon, but I am hoing the a7-100 comes out soon.

thanks,

DC

[jpeyron]

Hi @DigitalConfig,

The xdc would be here for the Arty-A7-35T then. Also Arthur reminded me about a better option then "make external". Select "Create Interface Port" instead. You have a lot more options for what you want and you can dictate what pin name the wrapper will use. 

cheers,

Jon