Genesys DDR2 + ISE

[Kimxin]

Hello,

I am a newbie in VHDL, so bear with me if my question is about rudimentary things. I am trying to use DDR2 on a Genesys board and have not had any success yet. After searching for a while on internet I could find this post  https://forum.digilentinc.com/topic/604-genesys-ddr-with-ise-147/

That made it clear how to solve the mismatch problem between pins. The example at the end of this page : https://reference.digilentinc.com/genesys:mig suggested by sLowe also works. However, that example just shows if phy_init_done goes high or not. I am looking for an example in ISE that simply writes a value in the memory and reads it. Actually I want to instantiate DDR2 in top level and use the DDR2 to get data from a port and save it.

I was looking at the example project for Genesys provided in the above link and in "ddr2_mem_if_top" file I saw that parameters are not for the memory on Genesys board, it is for 72-bit RDIMM design (for ML561 Reference board design).

I wonder if there is any simple example for the Genesys board that shows how to use DDR2, using ISE.

 

Thanks

 

[sLowe]

Hey Kimxin,

I don't know if any simple example exists for using the MIG. I think the Nexys4-DDR ram2ddr component https://reference.digilentinc.com/nexys4-ddr:sram  should expose you to using the DDR2 MIG interface. You may even be able to use that component if your design doesn't need to operate very quickly. I haven't worked directly with the MIG to read and write but I think a good place to start looking would be the ram2ddr component and the MIG user guide. (Found by opening the IP and clicking User Guide). 

If these resources don't help too much, I can spend some time to try and get a simple working demo. Although now that school has started back up it may take a little bit of time.

Good luck!