CMOS signals on Nexys Video FMC

[Souradeep Mitra]

In the Nexys Video Artix 7 board the FMC connector contains 34 differential pairs connected to the FPGA. Can I use two tracks of a differential pair as two single ended CMOS signals. Also can I configure LVDS pins and CMOS pins on a single I/O bank of the FPGA?

[zygot]

@Souradeep Mitra,

Yes, you can mix LVDS and single-ended IO on the same bank. Yes, you can use IO and PCB traces laid out differential pair as two single-ended IO. Those are the short and incomplete answers to your questions. In reality it's a lot more complicated.

The issue is that if the differential traces on the PCB are laid out specifically for differential, that is they are electro-magnetically coupled, then you can have one of those signals causing errors on the other if you use them as two single-ended signals. The errors will be near the switching transitions ( i.e. low-high, high-low). It is possible to lay out signal pairs that are loosely electro-magnetically coupled so that they can be used for either differential or single-ended. This is how the Altera HSMC specification handles this for some of the signals. Of course this strategy isn't optimal for either differential or single-ended signals.

Please DO read the Xilinx reference manuals about how IO and bank voltage works. You need to be aware of proper LVDS termination and the difference between HP and HR bank rules for Select IO resources. The Nexys Video IO are all HR banks. Pleas DO refer to the Nexys Video schematic.

Having said all of that I don't know that the Nexys Video FMC differential signals are actually laid out as differential signals. I have certainly used them ( On the Nexys Video ) as single-ended for many applications including 32-bit 100 MHz USB 3.0 controller interfaces.

Does any of this matter for your application? Yes, no, maybe maybe not.... all or one of those.

Hopefully, @elodg can tell us if the LA signals were laid out as strictly differential, strictly single-ended or something in between. I suspect that they are all single-ended but the gerbers aren't available for customers to check.

[elodg]

All Digilent FMC Carrier boards have User I/O pairs routed differentially, 100-ohm coupled. Artix-7 has HR banks, supporting LVDS_25 and many other differential standards. You may use single-ended standards too, like LVCMOS25. In this case, _P and _N traces will have crosstalk between them. Stronger coupling benefits differential noise rejection, but causes higher crosstalk between single-ended traces. In single-ended applications, depending on signal rise times, this might cause issues. In such cases use either _P or _N side for the useful signal and drive the other side with constant 0 or 1. It wastes pins, but helps with crosstalk.

As always, check the schematic, reference manual and SelectIO user guide. The latter for verifying different I/O standard compatibility in the same bank, supply and termination requirements.

[Souradeep Mitra]

Thank you @elodgand @zygot very much for the detailed response.

Actually in my application I need to route 43 CMOS signals alongwith 4 pairs of LVDS signals through the FMC connector. Hence, options are not available to me. In such a case is there any way to minimise the crosstalk between a pair of _P and _N signals used as two separate LVCMOS25 signals? Can you suggest any combatable stategy via proper routing or use of any passive component between the lines to cancel the coupled impedance?

Also there are two types of differential pairs in the FMC connector viz of the type of FMC_LA_P & FMC_LA_N and FMC_LA_CC_P & FMC_LA_CC_N. Is there any difference between these two types of differential pairs? Is there any advantage of using the _CC_ pins for LVDS25 signals?

[zygot]

@Souradeep Mitra,

There are some strategies. I suggest that you download schematics for a few FMC mezzanine boards ( FTDI and Cypress have USB development boards as examples ) to see how bus signals are assigned to pins. Say you have am 8-bit bus. You can assign them all to _p pins that aren't in close physical proximity ( but not too far either ). You can then assign the corresponding _n pins to GND. If you run out of IO you might be able to assign another signal to one of these _n pins if it is guaranteed not to switch in the same time frame as the bus. So, separation in distance and separation in time are possible strategies.

_CC pins can be connected to the FPGA clock routing resources so reserve these for clocks if there are any. Otherwise, the _n and _p IO's are equivalent in terms of single-ended signals.

Note the previous guidance to study and understand the appropriate reference material. IO banks powered by Vadj can have selectable voltages and these voltages decide what kinds of IO standards you can use and whether or not there is internal FPGA termination available for LVDS pairs ( so you don't have to add external terminators at less than optimal physical locations ).

There are more things to account for if you are designing your own FMC mezzanine board but I think that I've been reasonably generous with free advice. Though I would suggest having an experienced engineer do that. (I'm assuming from your questions that you are not such a person. ). You aren't going to be trained to do expert PCB design on a user forum but at least you might get an appreciation for the complexities involved. Along with FPGA vendor reference manuals, sometimes IC vendors supply good guidance on how their development boards are designed providing additional hints as to what's involved.

 

[Souradeep Mitra]

@zygot Thank you very much. This shall help a lot.

 

[elodg]

Deciding which signals could share coupled traces is I/O interface dependent. For example, if it is a source-synchronous parallel interface, crosstalk is not an issue between bits of the same data bus. All bits that change rise or fall in the same time, momentarily inducing change on coupled bits too. It all stabilizes quickly by the time the sampling clock edge arrives.  However clock is essential to be monotonic and not have spurious edges. So in this case I would make sure clock (if single-ended) is coupled with a GND trace.

[zygot]

13 hours ago, elodg said:

Deciding which signals could share coupled traces is I/O interface dependent. For example, if it is a source-synchronous parallel interface, crosstalk is not an issue between bits of the same data bus. All bits that change rise or fall in the same time

@elodg

I agree with you except that I'd add that the designer is responsible for ensuring that the data settles before the active clock edge. The Nexys Video board FMC LA PCB trace pair lengths ( is it 100 mils? I can't remember from a previous post concerning the Genesys2 FMC ...) are held to reasonably tight relative mismatch but the analysis extends to the mezzanine board as well. It does take some effort to ensure that interfaces with a lot of signal all meet setup and hold times.

In the case of a lot of simultaneously switching FGPA outputs there other noise sources that might not settle as quickly as expected.

[Souradeep Mitra]

@elodg That is a great suggestion. In that case the signal integrity of the clocks become very important. 

Thanks.

If the trace of the differential pair in the mezzanine card are drawn far apart would that decrease the coupling between the signals?

[zygot]

8 hours ago, Souradeep Mitra said:

If the trace of the differential pair in the mezzanine card are drawn far apart would that decrease the coupling between the signals?

All differential pair PCB traces are routed for a specific _n to _p impedance with respect to each other and ground and spaced far enough from neighbouring traces to minimize coupling. Yes, spacing long parallel runs of differential ( or single-ended signals for that matter ) properly will reduce coupling effects.

8 hours ago, Souradeep Mitra said:

the signal integrity of the clocks become very important

The signal integrity of all signals in an interface is important. Often you can get around deficiencies in the physical characteristics of signal traces for low performance applications with the FPGA implementation... but for high performance interfaces this isn't guaranteed.. so your ability to account for all parameters is important. An interface using a clock reference should be designed as a whole.

I strongly urge anyone intending to implement a high performance PCB acquaint themselves with the physics involved. Companies that do PCB design for a living have the software tools to track signal length and impedance calculations as well as other signal integrity concerns. Small companies and those on a tiny budget will have to do this on their own. If you intend to produce a product then limiting EMI is critical to meeting requirements of regulators like the FCC.