Memory tutorial

[dgottesm]

Hi

I am beginning my foray into FPGA design, and I decided that the best to to learn would be to learn on the go, and learn as I go.

I am using a Zybo Z7 7020, Windows 10, and Vivado 16.4

I have a project for school which will be using PMODs as IOs and the information will have to be saved to memory of the board

I am wondering if there is a good tutorial which will help me learn how to access, read and write to the DDR3

[D@n]

@dgottesm,

Working with DDR3 SDRAM is a common request on this forum--and the easy answer isn't very fulfilling, nor does it offer many further ideas to move from it.  See this previous post for a discussion of this issue.  Feel free to open up the .prj file for the Zybo to know what settings you might need,

Dan

[dgottesm]

Thanks @d@n

Is the standard way to access the DDR3 with the MIG on Vivado? Does Digilent offer its own solution?

I think my memory needs are simple. I want to implement a simple FIFO stack. Where is a good place for me to start to learn to do this?

[jpeyron]

Hi @dgottesm,

Accessing the DDR3 is typically done using the MIG. We do not off an alternative.  Here is some information on using a FIFO stack.

cheers,

Jon

[D@n]

@dgottesm,

This link has pictures. 

If your memory needs are simple, they can often be handled with block RAM.  You can declare block RAM within your design, and you will find it *exceptionally* easy to use and access.  The link above should discuss how to do a traditional FIFO in block RAM alone.  If, on the other hand, you need more block RAM memory than your chip has ... that's when you need to turn to the DDR3 solution.  I wouldn't touch it, though, if I only had a simple requirement.

Dan

[xc6lx45]

4 hours ago, D@n said:

... they can often be handled with block RAM. 

+1 for that. If possible, it'll save you a week, perform better and you maintain a board-independent design.

I'm sure there are lots of FIFO examples out there... Attached one I use. Expect e.g. around 150 MHz on speed grade 1 Artix, possibly faster.

Note, the memory is here ("inferred"):

reg [DATABITS-1:0] 	      mem[((1 << ADDRBITS)-1):0];

So there is no need to instantiate BRAM, it happens automatically.

FIFO.v