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anurag

create delay in verilog in cmod a7

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hello,

i am using cmod a7. i am trying to blink the led at 1 sec delay(using verilog language). please help me with the code and also let me know the frequency we will be using to create delay and at which pin will it be available. 

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Hello @anurag,

I will not writing you the entire code, because I am more an VHDL guy. But the idea and the algorithm is the same. A good idea is to use a clock based delay, in which for a chosen clock period you start to number clock cycles until you reach a value that satisfy your delay. So, the best way to create a delay is by using a counter, find out how many clock cycles you need to wait  in order to obtain the required delay, this depends to your clock period. In this case, the code should look something like this:

   always @ (posedge clk) begin
                if (counter == value_to_reach) begin // where value_to_reach is as it says the value to reach in order to obtain the desired delay
                               counter <= 0;// reset your counter
                               enable_delay = ~enable_delay ;// this toggles every time your required delay is attained. 
                end

              else begin
                             counter <= counter +1;// keep incrementing   
               end
      end

To go further than that, a good practice is to split your logic in half. For example, if you want a 1s delay, you can use the above algorithm to create your base time. In this case units of  seconds, and after that you only need to increment every time you reach the number of seconds that you want to delay. This give you the possibility to create even greater delays. And also splits your counter variable in smaller parts. Regarding the pins, if you look into the CMOD A7 constraints file you will find the clock pin declared as :  

## Clock signal 12 MHz
#set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_14 Sch=gclk
#create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {sysclk}];
 
 The constraint file creates the connection between the ports of your top level module and the FPGA’s pins. So, if you want to blink you led for a desired period of time, you only need to map the enable_delay  signal to one led from the constraint file. I hope me answer give you some clarification, an I look forward to hearing from you.
 
PS: Be sure to initialize value_to_reach and enable_delay to zero.
 
Best Regards,
 
Bogdan Vanca
 
 
 

 

 

 

 

 

  

Edited by BogdanVanca

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thank you Bogdan vanca , that was really helpful . I am able to blink the led ,now i am working on the delay period .

i am trying to blink the leds alternatively .if you can help me with that.

i really appreciate your help.

Edited by anurag

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Hello @anurag,

Try map enable_delay to one led and ~enable_delay to another one. And also for  a better understanding, I recommend to you to make a test-bench of your top level module.

Best Regards,

Bogdan Vanca

 

 

Edited by BogdanVanca

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dear bogdan

the code you provided earlier i am able to decrease/increase the brightness of led but not able to blink it properly(start -stop-start)

i did some test and found out that the if part of code is working but the else part is not

i.e.  if led is provided high in if part  and then low in else part when implemented the led stays high

and when reversed in coding and then implemented the led stays low only

.if you can help me with it

thanks

Edited by anurag

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Hi,

in Bogdan's code example, the "if..." clause runs once every (e.g.) 12 000 000 cycles.

The "else..." clause runs 11 999 999 times out of 12 000 000.

I think you're toggling the LED at a speed much faster than the human eye can follow, but effectively it's only on one half of the time, so it looks less bright.

 

If you allow me an opinion: Learn to use a simulator. "iverilog" is great, with "gtkwave". It takes an hour or two to get started, but you'll earn this time back within a day. It brings the bugs out in the light, with no place to hide (... warning: the baddest bugs don't fear the light... story for another day :))

And, more opinion: the first steps on the FPGA learning curve are near-vertical (new language, so many tools) but it flattens out eventually.
A guaranteed (but slow) way to get up: every time you don't understand something, dig down to the bottom unless it's obviously clear; don't leave any loose ends behind.

Edited by xc6lx45

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