Pujith Krishna Posted February 13, 2018 Share Posted February 13, 2018 getting an error while trying to program fpga using zybo board with pmod acl Link to comment Share on other sites More sharing options...
xc6lx45 Posted February 13, 2018 Share Posted February 13, 2018 Hi, did you build the bitstream for the correct device? Link to comment Share on other sites More sharing options...
Pujith Krishna Posted February 13, 2018 Author Share Posted February 13, 2018 Yes...i did it for correct device and i did the check in at include partial bit stream....if i uncheck that..it is showing FPGA intialization failed Link to comment Share on other sites More sharing options...
jpeyron Posted February 13, 2018 Share Posted February 13, 2018 Hi @Pujith Krishna, Can you please attach a screen shoot of you block design from Vivado. Did you alter anything in the zynq core besides adding a 50 mhz clock as I did in screen shot? Make sure to connect the new clock output from zynq core to the ext_spi_clk on the Pmod ACL IP core. Here is my completed project done in Vivado 2017.4 for the Zybo and ACL. It programs the fpga and runs the application. thank you, Jon Link to comment Share on other sites More sharing options...
Pujith Krishna Posted February 19, 2018 Author Share Posted February 19, 2018 hey @jpeyron actually the problem is with my software .When i try to use with vivado 2017.3,it is showing the errors.when i updated this it is working .. thank you Link to comment Share on other sites More sharing options...
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Pujith Krishna
getting an error while trying to program fpga using zybo board with pmod acl
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