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Hi @Pujith Krishna,

Can you please attach a screen shoot of you block design from Vivado. Did you alter anything in the zynq core besides adding a 50 mhz clock as I did in screen shot? Make sure to connect the new clock output from zynq core to the ext_spi_clk on the Pmod ACL IP core. Here is my completed project done in Vivado 2017.4 for the Zybo and ACL. It programs the fpga and runs the application.

thank you,




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