Cmod A7 Oscillator Part Number

[vr_brian]

Howdy,

Would Digilent be willing to publish the part number of the 12MHz oscillator used on the Cmod A7?

Wondering if the as-built oscillator accuracy is tight enough for a timing project or if I need to add something else at IC4 per:

https://forum.digilentinc.com/topic/2362-cmod-a7-oscillator-question/

Thanks,

 

Brian

[zygot]

@vr_brian,

Perhaps you would get better advice if you were to offer more complete information about your application requirements. Are you asking for help in doing the timing analysis or have specific questions with regard to a specific application requirement? There are IO pins on the CMOD A7 that can connect to an external clock source if you have tight timing requirements. This would be my short answer.

[vr_brian]

@zygot - just looking for the part number of the oscillator.  The second half was just a bit of info about why; not the clearest post on my part.  

[zygot]

@vr_brian,

No problem. The CMOD-A7 schematic has a part number. You really wouldn't expect to find a highly accurate, highly stable, low drift clock module on an inexpensive FPGA module would you?

I find it interesting that people with questions that they want answered are the most reluctant to answer questions posed to them.

Of course you are under no obligation to publicize any information at all.

happy FPGAing....

[xc6lx45]

Hi,

I believe the problem is that the part number is on the blanked-out page. It's probably shared with the FTDI chip.
Who has a PLL analyzer at home?

But, FYI: You can use a PLL to clean up the input clock  Ref: 7 series clocking guide page 73:

Jitter Filter
MMCMs and PLLs reduce the jitter inherent on a reference clock. The MMCM and PLL can
be instantiated as a standalone function to support filtering jitter from an external clock
before it is driven into the another block. As a jitter filter, it is usually assumed that the
MMCM and PLL will act as a buffer and regenerates the input frequency on the output (for
example, FIN = 100 MHz, FOUT= 100 MHz). In general, greater jitter filtering is possible by
using the MMCM attribute BANDWIDTH set to Low. Setting the BANDWIDTH to Low
can incur an increase in the static offset of the MMCM.

For example, I'm using an MMCM 12 MHz to 300 MHz, cascaded with a PLL 300 MHz to 125 MHz. The 300 MHz was the first number that came along (takes only a few mouse clicks in the clocking wizard, you may get better results if you hunt a bit for a cleaner division ratio) The numbers I've got on my screen are 480 ps input jitter for the 2nd stage input, and 126 ps for the output. So yes, it appears to do some filtering.

Any comments on this approach, please let me know. As it happens, my PLL analyzer has run out of electrons...

If you try this dual-stage approach (first must be MMCM because of the low input freq), make sure that the "Source" of the 2nd stage (page 1) is "global buffer" not "single ended clock capable ...". Otherwise the 2nd stage would cause a routing error.

 

[zygot]

@xc6lx45

I'm looking at the CMOD A7 schematic sheet 3 and IC4 is a 12 MHz oscillator module BUT the part number is ASEM1-100.00MHZ-LC-T. The output pin is connected to net USB-12MHZ. I suspect that the part number on the schematic is wrong and the net name is correct as 12 MHz would most likely the correct frequency for the programming interface and the Digilent master constraints file only has one clock pin assignment. I could be wrong ( wouldn't be the first thing I was every wrong about but here is no place to make detailed confessions...).

You are correct that multiple stages of PLLs are often used in commercial "clock cleaner" products to reduce jitter. Ageing drift, initial accuracy, temperature drift etc. are another matter. And of course there are a lot of types of jitter if that's what you need to account for.

Thanks for adding your commentary. If I post commentary that doesn't seem to be correct please do challenge it.

[xc6lx45]

@zygot

Hi,

I think I sometimes tend towards brevity instead of diplomacy... No disrespect intended, we're all here for fun and to learn. I'm just not too keen on writing long posts.
Now this oscillator question: Hate to disagree again but IC 4 is not assembled. It's an optional component, see picture.

R80 leads to a net labeled "USB 12 MHz", so it gets its clock from the USB chip unless the DNP component is added and the resistor is removed.

And, I suspect the OP was mainly interested in absolute timing accuracy, so my post on jitter may not really help...

 

[jpeyron]

Hi @vr_brian,

The specs of the oscillator are below.

Frequency Stability: +/- 25ppm
Aging: +/- 3ppm per year at 25C
Phase Jitter: <1 ps (max)

As mentioned above if you want to install your own oscillator in the IC4 location then you need to also remove R80. Here is a forum thread that discusses loading a 100 MHz oscillator to IC4.

cheers,

Jon
 

[vr_brian]

37 minutes ago, xc6lx45 said:

And, I suspect the OP was mainly interested in absolute timing accuracy, so my post on jitter may not really help...

Just frequency accuracy for the this project.  I'm sure the MMCM -> PLL jitter filter will find its way into a future design 

[zygot]

Hi @xc6lx45,

You are correct about IC4. Your eyesight is better than mine. GCLK referenced as sysclk on the master constraints file must indeed be sourced from the "page that cannot be displayed" as there are no other references to net GCLK, nor other reference to the net USE_12_MHZ in the schematics. Thanks for pointing this out. Typically I'd expect a DNP designator for IC4 to clarify this. There does appear to be an oscillator near the (presumed) FTDI chip but all of my magnifiers are currently packed away so I can't read it.

28 minutes ago, xc6lx45 said:

And, I suspect the OP was mainly interested in absolute timing accuracy, so my post on jitter may not really help...

I'm inclined to agree with you on this as well though I doubt that we'll ever know for sure as the person who started this thread is silent on the subject. Still the thread might be useful to someone.

I don't assume that challenging an argument implies disrespect. The goal is offer accurate consul. No disrespect inferred.

[vr_brian]

2 minutes ago, jpeyron said:

The specs of the oscillator are below.

Frequency Stability: +/- 25ppm
Aging: +/- 3ppm per year at 25C
Phase Jitter: <1 ps (max)

great, thanks Jon

[xc6lx45]

2 minutes ago, vr_brian said:

Just frequency accuracy for the this project.  I'm sure the MMCM -> PLL jitter filter will find its way into a future design 

Oh that's easy to fix. Just put it into a temperature-stabilized oven :-)

[zygot]

And then @jpeyron came along as I was writing the previous post and answered the question. The oscillator is better than I suspected that it would be.

[xc6lx45]

1 minute ago, zygot said:

And then @jpeyron came along as I was writing the previous post and answered the question. The oscillator is better than I suspected that it would be.

Agree... maybe I'll remove the jitter filter to improve the carbon footprint...

[zygot]

Sigh! I'm still curious about the general nature of Brian's application. But time to move on...