Unable to read the block memory content from a specific address

[Ajeeth]

Hi, I have been using IP core generator for block memory in Digilent NEXYS 4 ddr.

I'm able to write the data on to the block ram and retrieve back the data at same clock cycle.But, when i try to read the contents of ram at different extent the instantiation is taking a different block of the block ram. 

Anyone help me out with the instantiation technique.

Thank you

[xc6lx45]

Hi,

the code shows two instances (two completely independent RAM modules)...

If you dig up the VGA discussion from yesterday, you can find a Verilog RAM example there. You don't even need to use the IP core generator, it's enough to describe the functionality (so-called "inference").

[hamster]

Hi,

Once you get the feel for how FPGAs work, have a good look at the Vivado Synthesis Guide ( https://www.xilinx.com/support/documentation/sw_manuals/xilinx2017_1/ug901-vivado-synthesis.pdf ).

It has lots of design patterns for how to describe the sorts of structures you might want to use -without reaching for the library of primitives. It covers things like memories, DSP blocks, shift registers, fifos and so on - without using the IP generator.

It can be a great technique to use, as:

- it does not tie your logic designs to a vendor's IP libraries & licensing

- it allowing others to use your designs on different FPGA tools

- is more flexible than using IP blocks

- you don't need to regenerate IP blocks to make small changes

- Easier to integrate into source control systems like Git, compared with IP blocks

You might need to flick between other user guides (such as https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf for memories), but I am ure you will find it interesting.