How to use DDR3 on Xilinx Arty board?

[smallpond_admin]

I have been trying to use the MIG in Vivado to work with the Xilinx Arty on-board DDR3 chip. So far I have gotten nothing but errors and dead ends from tutorials and documentation. Does anyone know of the best and simplest way to communicate with the RAM?

[jpeyron]

Hi @smallpond_admin,

Here is a forum thread that discusses using the prj file for the mig and the Arty.  You can find the Arty Xilinx MIG Resources on the resource center for the Arty here. If you are ok with using microblaze then here is a tutorial with includes the DDR3 here. If you are trying to connect to the mig without using microblaze if would look at the Nexys 4 DDR Music Looper demo here as a potential reference.

thank you,

Jon

[smallpond_admin]

Thank you for the help. I have a custom design I need to interface with the DDR3.

[D@n]

@smallpond_admin,

It's a shame DDR3 SDRAM access is so complicated.  This is partly due to the inherent complexity of the controller necessary to handle the SDRAM, and partly due to the high speeds involved.

Digilent (not me) has tried to solve this issue by offering schematic based design solutions and tutorials, showing step by step how to get a fairly standard solution working.  These tutorials are great, until you want to do something that's a bit off of the beaten path.  Then, from my own observations of this forum, they fail miserably.

I've tried a different solution.  If you look at my own OpenArty project, I created the MIG controller and then interfaced to it from Verilog.  When I found the AXI interface too complex, I bridged to it from a *MUCH* simpler wishbone interface. This has made reading and writing SDRAM fairly easy for me, although it is by no means all that fast.  (The MIG controller has a very bad latency problem.)  It works, it's open source, you are welcome to try it yourself.  The problem with this approach is that it's not nearly as well documented as Digilent's approach--although I have put a document together describing how to set it up.

Feel free to let me know if you wish to use this approach and run into any questions or problems,

Dan

[zygot]

I certainly agree with D@n that DDR and SDRAM solutions provided by all of the FPGA vendors is more difficult than any reasonable user would like it to be. A number of simple SDRAM controller solutions with HDL code have been posted by various people over the years and might be fine for "hobby" projects. I would point out that none of these offers self-calibration nor do they constrain logic to specific locations appropriate to the IO connected to the external memory or take into account PCB trace characteristics. The vendor solutions do this. For simple designs operating at room temperature simple controllers will probably work just fine for most peoples' requirements. On the other hand FPGA vendors have reasons for "encouraging" users, both hobbyists and companies not wanting to expend the resources creating their own IP, to do FPGA development a certain way.....

If you delve into vendor provided designs for interfaces that have tight timing requirements ( Ethernet, external memory, etc ) operating near the upper range of IO frequencies you get a sense of how complicated these designs need to be.... and these still come with warnings not to use them for critical applications.

1 hour ago, D@n said:

This has made reading and writing SDRAM fairly easy for me, although it is by no means all that fast.  (The MIG controller has a very bad latency problem.

Gosh, I'd like to read a bit more detailed explanation of this comment.

[D@n]

@zygot,

Did you read the link that comment pointed to?  At the bottom is both a discussion of how much latency a DDR3 *should* have (as calculated by your most humble counterpart), and then a measurement of how much latency was measured in the AXI based MIG controller.  Feel free to ask if you have questions, although further discussion on this topic should probably be kept to another thread.

Dan

[zygot]

@D@n,

The completely honest answer is that I glanced through the text in your link but didn't see (notice ??) a reference to a "very bad latency" issue. I guess that the pairing of "not very fast" with the inference of needing low latency is curious to me. I'm not trying to be argumentative  (today...), just intrigued at what you might be implying in this context. The simple question that is the basis for this thread is actually an interesting question on a much more complex level.

P.S. I did notice the discussion about restrictions with regard to clocking.... blind as I am.

[zygot]

@smallpond_admin,

Just know that you aren't the only one who finds working with the MIG tool exasperating and difficult... especially if you want to make a small change to and existing design. Still it beats whatever INTEL ( aka Altera ) offers.