Axi DMA timing

[Weevil]

Hi all,

i am using the DMA to send data from my DDS-compiler to DDR on the Arty board. The data transfer works in general, but actual the timing is wrong.

My actual Design:

I generate a 2 Hz clock and transfer with 2 Hz values from the DDS to the DMA. The problem is, if i start the simple_poll-function from this code/design (http://i.imgur.com/7v0d7NF.png) it takes the same value many times.

So finally the aim is to get a value every time the DDS provides a new one.

Thanks to everyone who can help!

 

[jpeyron]

Hi @Weevil,

I am not very familiar with the DMA but looking at you SDK code on line 138 are you suppose to set all of the RxBufferPtr's to 0xCC?

thank you,

Jon

[Weevil]

@jpeyron

thank you very much for your comment!

i expected it would be necessary to "null" the RxBufferPtr because there are datas left from the transfer before (but i am new in this and not sure with it). I tested to delet this function and the output changed, but it did not solve my problem.

[jamey.hicks]

You should use the 2Hz clock for m_axi_s2mm_aclk, otherwise, I expect you are seeing approximately 83000/2 repeats of the same value. The tlast value should also be driven from the same clock as tdata so that it will be in sync as well.

 

 

[Weevil]

@jamey.hicks

I did as you suggested, but now i got the warning:

• [BD 41-1363] The clock pins '/microblaze_0_axi_periph/S03_ACLK' (interface '/microblaze_0_axi_periph/S03_AXI') and '/axi_dma_0/m_axi_s2mm_aclk' (interface '/axi_dma_0/M_AXI_S2MM') must be connected to the same source

...if i now do this connection as described i get the following error:

• [BD 41-237] Bus Interface property FREQ_HZ does not match between /microblaze_0_axi_periph/s03_couplers/auto_us/S_AXI(10000000) and /axi_dma_0/M_AXI_S2MM(83333333)

 

Attached my actual design:

[jpeyron]

Hi @Weevil,

Here is a xilinx forum thread that is dealing with a similar error and has a solution for their situation.

cheers,

Jon

[jamey.hicks]

The aclk of dds_compiler_0 should be the same as the m_axi_s2mm_aclk, judging by the pinouts.

It confuses me that tlast is coming from a clock generator. Shouldn't it be driven by an output from dds_compiler_0 along with tdata and tvalid?

 

[jamey.hicks]

Take a look at the configuration options for DDS -- it has an option to enable the tlast pin on the AXI stream interface.

 

[Weevil]

@jamey.hicks and @jpeyron

Thank you very much for your comments.

I got it to work.

I changed the MAX_PKT_LEN_WORDS to 1 and the MAX_PKT_LEN to MAX_PKT_LEN_WORDS*8

With the design and uart configuration to Baudrate 460800 i got a constant stream of 100 kHz and 32bit integers. I think a higher speed also would be possible, for mit it is enough.

 

[jamey.hicks]

Nice job! I'm happy to hear that you got it working.